> -Original Message-
> From: Alex Bennée
> Konrad Schwarz writes:
>
> > static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
> > {
> > RISCVCPU *cpu = RISCV_CPU(cs);
> > @@ -163,21 +167,33 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs,
> > int base_reg)
>
Hi,
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 5, 2022 0:02
> To: Schwarz, Konrad (T CED SES-DE) ;
> qemu-devel@nongnu.org
> Cc: Alistair Francis ; Bin Meng
> ; Palmer Dabbelt
> ; Ralf Ramsauer
> Subject: Re: [PATCH
Hi,
> -Original Message-
> From: Alistair Francis
> Sent: Tuesday, January 4, 2022 23:12
> To: Schwarz, Konrad (T CED SES-DE)
> Subject: Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver
>
> On Wed, Jan 5, 2022 at 1:56 AM Konrad Schwarz
> wrote:
> > dif
> -Original Message-
> From: Alistair Francis
> Sent: Tuesday, January 4, 2022 23:03
> On Wed, Jan 5, 2022 at 1:55 AM Konrad Schwarz
> wrote:
> >
> > This is analog to the existing 'info mem' command and is implemented
> > using the same machinery.
> > hmp-commands-info.hx |
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, January 4, 2022 21:57
> Subject: Re: [PATCH v2 1/5] RISC-V: larger and more consistent register set
> for 'info registers'
>
> On 1/4/22 7:51 AM, Konrad Schwarz wrote:
> > static const int dump_csrs[] = {
> > +
>
Since version 0.8.2, QEMU includes the processor affinity
fix. Did you try with this version ?
No, I branched off at 0.8.0. Is my assumtion correct that the problem
lies in the way asynchronous events (interrupts) are signaled to the
interpreter loop?
Regards,
Konrad
Hi,
I have a brand new dual core machine which caused QEMU to go into an
endless loop under Windows XP. Modifying the process affinity mask to
restrict the process to run on only one machine made the problem go
away. I admit to having rewritten the main loop event handling code
so it may well
Hi,
gdb 5.2.1 (which is
what comes with MinGW/MinSys) is crashing quite a lot. Is this the normal
state of affairs, or am I doing something wrong? Should I be developing
under Linux?
Regards,
Konrad
BEGIN:VCARD
VERSION:2.1
N:Schwarz;Konrad
FN:Konrad Schwarz
ORG:Siemens AG;CT SE 2
Another question:
Am I allowed to change the Makefile CFLAGS value from -O2
to -O0?
Regards,
Konrad
From: Schwarz, Konrad Sent: Friday,
March 03, 2006 5:02 PMTo:
'qemu-devel@nongnu.org'Subject: Debugging under
MinGW
Hi,
gdb 5.2.1 (which
is what comes with MinGW
Hello,
http://fabrice.bellard.free.fr/qemu/qemu-doc.html#SEC10documents
the-serial dev
option as accepting
thefile:filenameoption but does not mention that this is supported under Linux only.Regards,Konrad Schwarz
___
Qemu-devel mailing list
Also note that qemu isn't even vaguely cycle accurate, and
doesn't accurately model TLB or cache. It should be
sufficient for most applications, but code that does sneaky
hardware specific things (like assuming a particular TLB size
or relying on cache/TLB lockdown for correct behavior)
I have a telnet character device for QEMU for Windows. That means that
you can hook up an arbitrary emulated character device (terminal) to a
Telnet connection.
Unfortunately, the code uses a heavily modified Windows event loop and a
very slightly extended character device interface. For my
Date: Tue, 18 Apr 2006 21:54:42 +0200
From: Stefan Weil [EMAIL PROTECTED]
Subject: [Qemu-devel] Flash simulation
To: qemu-devel@nongnu.org
Message-ID: [EMAIL PROTECTED]
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
A typical embedded system (and also most standard PCs)
-Original Message-
From: Paul Brook [mailto:[EMAIL PROTECTED]
On Monday 10 April 2006 12:26, Schwarz, Konrad wrote:
Hello,
this patch adds support for the Altera Excalibur device (an
FPGA that
supports the ARM922T core).
Are there any plans to update the linux kernel support
To: qemu-devel@nongnu.org
Message-ID: [EMAIL PROTECTED]
CVSROOT: /sources/qemu
Module name: qemu
Branch:
Changes by: Fabrice Bellard [EMAIL PROTECTED]
06/04/12 20:21:17
Modified files:
. : vl.c vl.h
Log message:
win32 serial port
Hello,
this is to inform you that I have extended the QEMU ARM emulation to
support coprocessor 14, as implemented in the Embedded ICE version
0b0010. This coprocessor implements the debug communications channel,
which is usually used to communicate via a JTAG-based hardware debugger.
One such
Hi,
One of the changes I
would like to contribute (assuming my company gives the ok) is a somewhat
improved reader forELF executables, and returns the entry point.
Although somewhat useless for the bootstrap program (which must start at the
processor's reset address), this is useful to
This fixes an omission in the documentation:
diff -c -r1.1 qemu-doc.texi
*** qemu-doc.texi 2006/02/16 09:32:42 1.1
--- qemu-doc.texi 2006/03/20 15:56:04
***
*** 432,437
--- 432,438
[Linux only, parallel port only] Use host parallel port
@var{N}. Currently
-Original Message-
From: Paul Brook [mailto:[EMAIL PROTECTED]
Sent: Tuesday, March 14, 2006 3:21 PM
To: qemu-devel@nongnu.org
Cc: Schwarz, Konrad
Subject: Re: [Qemu-devel] Questions on ARM port
Basically, r3 is initialized by start+8 (to 0x8, in
my case).
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