Hi Peter,
unfortunately you are right.
The correct line is this:
/* invalidate lock */
-env->cpu_lock_addr = -1;
+env->lock_addr = -1;
I am sorry. It was most likely the last line which I added. But I
forgot, that I disabled the system emulation already.
Therefore my make proces
Hi Jia,
On 1/26/2015 10:50 AM, Jia Liu wrote:
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke wrote:
From: Christian Svensson
This patch adds support for atomic locks
and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via
From: Christian Svensson
This patch adds support for atomic locks
and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock implementation of musl
Signed-off-by: Christian Svensson
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks for a zero offset and optimizes it.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c
This patch adds the new atomic operations of the
Load-link/store-conditional type which are called
l.lwa and l.swa.
For a cleaner implementation, all load and store instructions
are separated to a function.
Christian Svensson (1):
target-openrisc: Add l.lwa/l.swa support
Sebastian Macke (1
On 30/10/2013 3:02 PM, Richard Henderson wrote:
On 10/30/2013 02:08 PM, Sebastian Macke wrote:
Do you have a publicly accessible tree with all your patches applied?
I'd like to re-read the logic in the proper context.
After you are the second who demanded it:
https://github.com/s-macke
On 30/10/2013 12:47 PM, Richard Henderson wrote:
On 10/30/2013 12:07 PM, Sebastian Macke wrote:
case JUMP_BRANCH:
{
int l1 = gen_new_label();
-tcg_gen_brcondi_tl(TCG_COND_NE, dc->btaken, 0, l1);
+tcg_gen_brcondi_tl(TCG_COND_NE, jmp_pc
On 30/10/2013 11:14 AM, Richard Henderson wrote:
On 10/29/2013 12:04 PM, Sebastian Macke wrote:
The carry and overflag and the instructions l.addc and l.addic
are never used in the toolchain. Linux and gcc compiled software
don't need them.
Really? That's quite surprising.
Y
On 30/10/2013 11:33 AM, Richard Henderson wrote:
On 10/29/2013 12:04 PM, Sebastian Macke wrote:
{
int lab = gen_new_label();
-dc->btaken = tcg_temp_local_new();
-tcg_gen_movi_tl(jmp_pc, dc->pc+8);
-tcg_gen_movi_tl(dc->
On 29/10/2013 3:55 PM, Max Filippov wrote:
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke wrote:
On 29/10/2013 1:05 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke
wrote:
Additional this patch solves a severe bug for the softmmu emulation.
The pc has to be saved
On 29/10/2013 3:20 PM, Max Filippov wrote:
On Wed, Oct 30, 2013 at 1:53 AM, Sebastian Macke wrote:
On 29/10/2013 2:01 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke
wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
A
On 29/10/2013 12:47 PM, Peter Maydell wrote:
On 29 October 2013 19:04, Sebastian Macke wrote:
The TLB flush is not necessary as the mmu_index field
already takes care of correct memory locations.
Instead the tb flag field must be expanded that
the exception takes the correct translation block
On 29/10/2013 2:25 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
Instead of testing the overflow exception dynamically every time
The flag will be reckognized by the tcg as changed code and
will recompile the code with the correct checks.
Signed-off-by
On 29/10/2013 2:01 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
At the end of the TLB miss handler a tlb_flush of QEMUs TLB
is executed which is exactly what we want to
On 29/10/2013 1:05 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks
On 29/10/2013 2:15 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
srf is a boolean variable.
Therefore the instruction should check for != 0 and not for != SR_F
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 2 +-
1 file changed, 1
On 29/10/2013 2:15 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
Hi,
This is the second part of the patches to make the openrisc target faster
and more reliable.
Hi Sebastian,
this series doesn't apply cleanly to the current qemu git head,
what tree
srf is a boolean variable.
Therefore the instruction should check for != 0 and not for != SR_F
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index
The former patch which removed npc and ppc also removed the part in
which the registers were send to gdb. But the npc parameter
is necessary and the numbering of registers is fixed within gdb.
The correct npc value is the current pc value.
Signed-off-by: Sebastian Macke
---
target-openrisc
This patch enables single step debugging in gdb
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index ea007c7..d0d410a 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
Signed-off-by: Sebastian Macke
---
linux-user/openrisc/syscall_nr.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/openrisc/syscall_nr.h b/linux-user/openrisc/syscall_nr.h
index f4ac91e..72cbcf8 100644
--- a/linux-user/openrisc/syscall_nr.h
+++ b/linux-user
t together with the delayed slot flag
an additional branch flag is saved to differ between slot types.
In average the speed increases by around 5%.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 7 ---
target-openrisc/translate.c | 34 +
the uClibc library because of a segmentation fault.
E.g. when setting the locale. But this failure existed also before my patches
and is maybe not related to the target.
Best Regards
Sebastian
Sebastian Macke (13):
target-openrisc: Implement translation block chaining
target-openrisc: Separate
Instead of testing the overflow exception dynamically every time
The flag will be reckognized by the tcg as changed code and
will recompile the code with the correct checks.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 3 +-
target-openrisc/translate.c | 78
c and l.addc
This cpu violate the specification and will not run through the
test cases but increases the emulation speed between 20% and 200%.
The cpu is activated by the option "-cpu or1200-noflags"
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.c | 15 +--
To increase the readability the delayed slot handling is separated to
a function
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 46 +
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/target-openrisc/translate.c b
Very often the delayed slot flag is set only to be removed
one instruction later. This patch sets this flag
only on instructions which could fail and at the end
of a translation block if necessary.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 6 +-
1 file changed, 5
.
The pc has to be saved as these instructions can fail and lead
to a tlb miss exception.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 130 ++--
1 file changed, 76 insertions(+), 54 deletions(-)
diff --git a/target-openrisc/translate.c
patch, I choose solution no. 2.
If the first TLB register is cleared the whole TLB is cleared.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 2 +-
target-openrisc/interrupt_helper.c | 8
target-openrisc/sys_helper.c | 4
3 files changed, 5 insertions(
The TLB flush is not necessary as the mmu_index field
already takes care of correct memory locations.
Instead the tb flag field must be expanded that
the exception takes the correct translation block.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 4 ++--
target-openrisc
the delayed slot is executed.
btaken: temporary flag if the branch is taken or not
j_target: jump pc value
j_type: Save the type of jump. Static, dynamic or branch
The speed is increased by around a factor 2-3.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 40
Ok, thanks for the info.
For me it looks like removing the whole path code and putting a one-liner
combining two string is the best solution. But maybe I am missing something.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://b
Public bug reported:
If I run qemu user emulation with -L /path/to/my/sysroot/ in which also
the proc and dev filesystem is mounted QEMU eats my memory until it gets
killed by the kernel.
According to the strace output it follows the symbolic links in the proc
filesystem running forever in a recu
On 25/10/2013 5:21 PM, Jia Liu wrote:
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke wrote:
On 22/10/2013 8:47 PM, Jia Liu wrote:
Hi Sebastian,
On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke
wrote:
This series is the first part to make the OpenRISC target more
reliable and faster.
It
On 22/10/2013 8:47 PM, Jia Liu wrote:
Hi Sebastian,
On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke wrote:
This series is the first part to make the OpenRISC target more
reliable and faster.
It corrects several severe problems which prevented the OpenRISC emulation
for being useful in the
On 22/10/2013 9:01 AM, Max Filippov wrote:
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke wrote:
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have to
compile the image for QEMU anyhow.
http://opencores.org/or1k/OpenRISC_GNU_tool_chain
Then it's jus
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have
to compile the image for QEMU anyhow.
http://opencores.org/or1k/OpenRISC_GNU_tool_chain
Then it's just an "make && make test" in the corresponding
tests/tcg/openrisc folder.
Inside the virtual machine it would b
estep mode.
Because they are no longer needed and decrease the performance by using
two tcg instructions per opcode they are removed.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 2 --
target-openrisc/gdbstub.c | 16 ++--
target-openrisc/interrupt_hel
The branch flag is very often used. To increase the speed
the flag is separated. This patch removes several
ands and ors and branches from the generated code.
The additional flag btaken is no longer necessary.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.c | 1 +
target
The clock value is only evaluated when really necessary reducing
the overhead of the timer handling.
This also solves a problem in the way the Linux kernel
handles the timer and the expected accuracy.
The old version could lead to inaccurate timings.
Signed-off-by: Sebastian Macke
---
hw
Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.
Signed-off-by: Sebastian Macke
---
target-openrisc/mmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 22d7cbe..dd487bd
The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.
Signed-off-by: Sebastian Macke
---
target-openrisc/sys_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ope
The test cases did not correctly test for the carry flag.
Signed-off-by: Sebastian Macke
---
tests/tcg/openrisc/test_addc.c | 8 +---
tests/tcg/openrisc/test_addic.c | 10 ++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/openrisc/test_addc.c b/tests/tcg
this special case.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 50 -
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8908a2e..8276ce7 100644
--- a/tar
This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.
Tested by checking crashing programs which otherwise work in or1ksim.
Signed-off-by: Sebastian Macke
---
target
in one of the future patches.
Only the patch which removes the npc and ppc variables removes a little feature
from the OpenRISC target but which does not break the specification and will
lead to
a significant speed improvement.
Sebastian Macke (9):
target-openrisc: Speed up move instruction
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 45 ++---
1 file changed, 26
The branch flag is very often used. To increase the speed
the flag is separated. This patch removes several
ands and ors and branches from the generated code.
The additional flag btaken is no longer necessary.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.c |1
The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.
Signed-off-by: Sebastian Macke
---
target-openrisc/sys_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/t
The clock value is only evaluated when really necessary reducing
the overhead of the timer handling.
This also solves a problem in the way the Linux kernel
handles the timer and the expected accuracy.
The old version could lead to inaccurate timings.
Signed-off-by: Sebastian Macke
---
hw
This patch corrects several rare bugs during an interrupt process.
Most of the time the pc is already correct and therefore no special
treatment of the exception type is necessary.
Tested by checking crashing programs which otherwise work in or1ksim.
Signed-off-by: Sebastian Macke
Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.
Signed-off-by: Sebastian Macke
---
target-openrisc/mmu.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 22d7cbe..dd487bd
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if/else chaining.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 46
---
1 file changed
his special case.
Signed-off-by: Sebastian Macke
---
target-openrisc/translate.c | 50
+++
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8908a2e..8276ce7 100644
--- a/tar
Hi Jia,
On 10/1/2013 10:33 PM, Jia Liu wrote:
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke wrote:
Hi,
this patch corrects two problems for the OpenRISC Target in QEMU. The first
one corrects one obvious bug
concerning the handling of page faults while reading from a page
the newest Linux kernel and compared the
output with or1ksim.
Sebastian
>From 4491bae7109e2b4de5a8de8a7e4b08d1f19ac70e Mon Sep 17 00:00:00 2001
From: Sebastian Macke
Date: Tue, 1 Oct 2013 21:39:38 -0700
Subject: [PATCH] Correction of the TLB handling of the OpenRISC target
This patch correct
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