Hi Joel,
I am away and wont be able to have too much time to look at this.
But have a few comments below and questions.
- You sent this 2 times, is the only change in v2 the sender address?
On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote:
> In the existing design, TTCR is
On Thu, Aug 10, 2023 at 09:35:18AM +0300, Michael Tokarev wrote:
> 09.08.2023 23:34, Stafford Horne пишет:
> > The architecture specification calls for the EPCR to be set to "Address
> > of next not executed instruction" when there is a floating point
> > exception
address when handling floating
point exceptions.
Stafford Horne (1):
target/openrisc: Set EPCR to next PC on FPE exceptions
target/openrisc/interrupt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson
Signe
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson
Signe
On Sun, Jul 30, 2023 at 10:43:45AM -0700, Richard Henderson wrote:
> On 7/29/23 14:08, Stafford Horne wrote:
> > The architecture specification calls for the EPCR to be set to "Address
> > of next not executed instruction" when there is a floating point
> > excep
On Sat, Jul 29, 2023 at 10:08:51PM +0100, Stafford Horne wrote:
> The architecture specification calls for the EPCR to be set to "Address
> of next not executed instruction" when there is a floating point
> exception (FPE). This was not being done, so fix it by using the same
x I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Signed-off-by: Stafford Horne
---
target/
architecture spec updates:
- Allow FPCSR to be accessed in user mode
- Select tininess detection before rounding
- Fix FPE Exception PC value
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/fpu_helper.c b/target
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Remove setting default NaN behavior.
target/openrisc/cpu.c | 4
1 file changed, 4 insertions
tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target/openrisc: Setup FPU for detecting tininess before rounding
target/openrisc/cpu.c| 4 ++
target/openrisc/fpu_helper.c | 13
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
Since v2:
- Add reviewed-by
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13
On Wed, May 10, 2023 at 05:16:20PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > Since
On Wed, May 10, 2023 at 05:13:03PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong
> > rb)
> > {
> > -#ifndef CONFIG_USER_ONLY
> > OpenRISCCPU *cpu
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
Since v1:
- Remove setting default NaN behavior. I discussed with the FPU developers and
they mentioned the OpenRISC hardware should be IEEE compliant when handling
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
Since v1:
- Use function do_fpe (similar to do_range) to raise exception.
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff
as no-ops as the cpu implementations do. As mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
Since v1
+openrisc
> + ~ (/qemu)?((/include)?/hw/openrisc/.*|/target/openrisc/.*)
This looks good to me for OpenRISC. Where can we view the coverity reports?
Is it this?: https://scan.coverity.com/projects/378
Acked-by: Stafford Horne
> +xtensa
> + ~ (/qemu)?((/include)?/hw/xtensa/.*|/target/xtensa/.*)
On Wed, May 03, 2023 at 10:41:42AM +0100, Richard Henderson wrote:
> On 5/3/23 10:14, Stafford Horne wrote:
> > > > +set_default_nan_mode(1, >env.fp_status);
> > > > +set_float_detect_tininess(float_tininess_before_rounding,
> > > > +
On Wed, May 03, 2023 at 08:37:31AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > OpenRISC defines tininess to be detected before rounding. Setup qemu to
> > obey this.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > targe
On Wed, May 03, 2023 at 08:36:13AM +0100, Richard Henderson wrote:
> On 5/2/23 19:57, Stafford Horne wrote:
> > @@ -55,6 +56,9 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
> > if (tmp) {
> > env->fpcsr |= tmp;
> >
On Tue, May 02, 2023 at 07:57:29PM +0100, Stafford Horne wrote:
> As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
>
> Update mtspr and mfspr helpers to support this by moving the is_user
> check into the helper.
>
> There is a logic change here to no longe
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
---
target/openrisc/fpu_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..1feebb9ac7 100644
instruction exception is not part of the spec, so this should be OK.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
---
target/openrisc/sys_helper.c | 45 +-
target/openrisc/translate.c | 72
OpenRISC defines tininess to be detected before rounding. Setup qemu to
obey this.
Signed-off-by: Stafford Horne
---
target/openrisc/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa..cdbff26fb5 100644
--- a/target
. As mentioned
series changes FPCSR read/write to follow the spec.
The series has been tested with the FPU support added in glibc test suite and
all math tests are passing.
Stafford Horne (3):
target/openrisc: Allow fpcsr access in user mode
target/openrisc: Set PC to cpu state on FPU exception
target
has been
> added, so that we have a pointer to that copy of the FDT.
This looks good to me.
Acked-by: Stafford Horne
> Cc: Stafford Horne
> Signed-off-by: Jason A. Donenfeld
> ---
> hw/openrisc/boot.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/ope
-by: Stafford Horne
---
target/openrisc/cpu.c| 1 -
target/openrisc/sys_helper.c | 7 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -98,7
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50
When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
target/openrisc
with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak | 1 +
hw
. Global cpu timer (last_clk and ttcr) reset, attached to the first
cpu only.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 116 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++---
include
Donenfeld
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9a78234a28..f8a68a6a6b 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -8,6 +8,7 @@
#inc
ent Vivier
Reviewed-by: Anup Patel
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/m68k/virt.c| 1 +
hw/rtc/goldfish_rtc.c | 37 ++-
include/hw/rtc/goldfish_rtc.h | 2 ++
3 files changed, 31 insertions(+), 9 deletion
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--
include:
- New virt plaform with, virtio and pci bus support
- OpenRISC support for MTTCG
- Goldfish RTC device endianness is configurable now
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Stafford Horne (10
On Fri, Jul 29, 2022 at 04:42:54PM -0700, Richard Henderson wrote:
> On 7/29/22 16:01, Stafford Horne wrote:
> > This patch enables multithread TCG for OpenRISC. Since the or1k shared
> > syncrhonized timer can be updated from each vCPU via helpers we use a
> > mutex t
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2;
- Added Reviewed-by
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
Since v2:
- Removed cpu_openrisc_timer_has_advanced lock optimization, measuring revealed
ent Vivier
Reviewed-by: Anup Patel
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
- Changed from enum property to boolean as suggested by Richard
hw/m68k/virt.c| 1 +
hw/rtc/goldfish_rtc.c | 37 ++-
include/hw/rtc/gold
Donenfeld
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index 9a78234a28..f8a68a6a6b 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt
When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/Kconfig | 3 +
hw
protection mapping then falling back to PAGE_EXEC.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes, added Reviewed-by
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/m
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106
-by: Stafford Horne
---
Since v2:
- Added Reviewed-by
target/openrisc/cpu.c| 1 -
target/openrisc/sys_helper.c | 7 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
. Global cpu timer (last_clk and ttcr) reset, attached to the first
cpu only.
Signed-off-by: Stafford Horne
---
Since v2:
- Moved timer init from init to reset suggested by Richard
hw/openrisc/cputimer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git
with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
Since v2:
- No changes
configs/devices/or1k-softmmu
seed to fdt
Stafford Horne (10):
hw/openrisc: Split re-usable boot time apis out to boot.c
target/openrisc: Fix memory reading in debugger
goldfish_rtc: Add big-endian property
hw/openrisc: Add the OpenRISC virtual machine
hw/openrisc: Add PCI bus support to virt
hw/openrisc: Initialize
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> >
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > -.read = goldfish_rtc_read,
> > -.write = goldfish_rtc_write,
> > -.endianness = DEVICE_NAT
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
>
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > -cpu_openrisc_count_update(cpu);
> > +if (cpu_openrisc_timer_has_advanced(cpu)) {
> > +
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewed-by: R
Signed-off-by: Stafford Horne
---
docs/system/openrisc/cpu-features.rst | 15 ++
docs/system/openrisc/emulation.rst| 17 +++
docs/system/openrisc/or1k-sim.rst | 43
docs/system/openrisc/virt.rst | 50 +++
docs/system/target-openrisc.rst
From: "Jason A. Donenfeld"
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne
Signed-off
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17
. This is not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Signed-off-by: Stafford Horne
---
target/openrisc
with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak | 1 +
hw
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne
---
hw/openrisc/cputimer.c | 1 +
1 file
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier
Signed-off-by: Stafford Horne
---
hw/rtc/goldfish_rtc.c | 46 ---
include/hw/rtc/goldfish_rtc.h | 2 ++
2 files changed, 39 insertions
since v1:
- Dropped semihosting support
- Added PCI support
- Added OpenRISC documentation
- Added OpenRISC support for MTTCG
- Support Configurating Goldfish RTC endianness
- Added a few bug fix patches
-Stafford
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Stafford
protection mapping then falling back to PAGE_EXEC.
Signed-off-by: Stafford Horne
---
target/openrisc/mmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
++
These will be shared with the virt platform.
Reviewed-by: Richard Henderson
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 117 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++---
include
n Linux 5.19-rc2.
>
> Cc: Stafford Horne
> Signed-off-by: Jason A. Donenfeld
> ---
> Changes v1->v2:
> - This is rebased on top of your "or1k-virt-2" branch.
> - It makes the change to the new "virt" platform, since that's where it
> makes most
n Linux 5.19-rc2.
>
> Cc: Stafford Horne
> Signed-off-by: Jason A. Donenfeld
> ---
> hw/openrisc/openrisc_sim.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
> index 35adce17ac..41821b5f30 10
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier
Cc: Arnd Bergmann
Signed-off-by: Stafford Horne
---
In a recent mail thread[0] it was discussed that future users of goldfish
devices
should use little-endian rather than native
On Tue, Jun 07, 2022 at 11:43:08AM +0100, Peter Maydell wrote:
> So I don't have a strong view on whether these devices should
> be DEVICE_NATIVE_ENDIAN or DEVICE_LITTLE_ENDIAN (except that
> my impression is that a DEVICE_LITTLE_ENDIAN device on a
> big-endian system is a bit weird, because it
On Tue, Jun 07, 2022 at 10:42:08AM +0200, Arnd Bergmann wrote:
> On Tue, Jun 7, 2022 at 10:11 AM Geert Uytterhoeven
> wrote:
> > On Sun, Jun 5, 2022 at 9:32 AM Stafford Horne wrote:
> > > On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote:
> > &g
On Sun, Jun 05, 2022 at 10:58:14AM +0900, Stafford Horne wrote:
> On Fri, Jun 03, 2022 at 09:05:09AM +0200, Geert Uytterhoeven wrote:
> > Hi Stafford,
> >
> > On Thu, Jun 2, 2022 at 9:59 PM Stafford Horne wrote:
> > > On Thu, Jun 02, 2022 at 09:08:52PM +
On Thu, Jun 02, 2022 at 11:42:30AM +, Joel Stanley wrote:
> Hi Stafford,
>
> On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
> >
> > This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
> > platform allows for a convenient CI platform for to
On Fri, Jun 03, 2022 at 09:05:09AM +0200, Geert Uytterhoeven wrote:
> Hi Stafford,
>
> On Thu, Jun 2, 2022 at 9:59 PM Stafford Horne wrote:
> > On Thu, Jun 02, 2022 at 09:08:52PM +0200, Geert Uytterhoeven wrote:
> > > On Thu, Jun 2, 2022 at 1:42 PM Joel Stanley wrote
On Thu, Jun 02, 2022 at 08:39:21AM -0700, Richard Henderson wrote:
> On 5/27/22 10:27, Stafford Horne wrote:
> > +void do_or1k_semihosting(CPUOpenRISCState *env, uint32_t k);
> ...
> > +DEF_HELPER_FLAGS_2(nop, 0, void, env, i32)
>
> Just call the helper &
On Thu, Jun 02, 2022 at 09:08:52PM +0200, Geert Uytterhoeven wrote:
> Hi Joel,
>
> On Thu, Jun 2, 2022 at 1:42 PM Joel Stanley wrote:
> > On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
> > > This patch add the OpenRISC virtual machine 'virt' for OpenRISC. Th
with up to 8 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated RTC to automatically configure the guest kernel
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak | 1 +
hw/openrisc
unimplemented semihosting calls will have side effects and return
results in register r11.
Signed-off-by: Stafford Horne
---
configs/devices/or1k-softmmu/default.mak | 2 +
qemu-options.hx | 16 ---
target/openrisc/cpu.h| 2 +
target/openrisc
These will be shared with the virt platform.
Signed-off-by: Stafford Horne
---
hw/openrisc/boot.c | 127 +
hw/openrisc/meson.build| 1 +
hw/openrisc/openrisc_sim.c | 106 ++-
include/hw/openrisc/boot.h | 34
etc do.
Stafford Horne (3):
target/openrisc: Add basic support for semihosting
hw/openrisc: Split re-usable boot time apis out to boot.c
hw/openrisc: Add the OpenRISC virtual machine
configs/devices/or1k-softmmu/default.mak | 3 +
hw/openrisc/Kconfig | 9 +
hw
On Sun, May 15, 2022 at 04:12:50PM -0700, Richard Henderson wrote:
> On 5/14/22 18:39, Stafford Horne wrote:
> > The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
> >
> >Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into
&g
-by: Stafford Horne
---
target/openrisc/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dfbafc5236..41d1b2a24a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#inc
From: "Jason A. Donenfeld"
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne
Signed-off-by: Jason A. Donenfeld
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horn
Donenfeld
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 6873124f74..35adce17ac 100644
--- a/h
From: "Jason A. Donenfeld"
The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.
Cc: Staf
Stafford Horne (1):
target/openrisc: Do not reset delay slot flag on early tb exit
hw/openrisc/openrisc_sim.c | 28 +++-
target/openrisc/cpu.c | 11 +++
2 files changed, 30 insertions(+), 9 deletions(-)
Jason A. Donenfeld (3):
hw/openrisc: page-align
On Wed, May 11, 2022 at 07:11:20PM -0700, Richard Henderson wrote:
> On 5/11/22 15:34, Stafford Horne wrote:
> > In this case I don't see how the tb->flag would be updated, ooh, I guess it
> > would have been set earlier when the TB was generated. Maybe that is what
&g
On Wed, May 11, 2022 at 02:56:37PM -0700, Richard Henderson wrote:
> On 5/11/22 14:43, Stafford Horne wrote:
> > At this point how would tb->flags have the right value? Would it always be
> > set
> > correctly by `cpu_get_tb_cpu_state` in the `lookup_tb_ptr`call?
&g
On Wed, May 11, 2022 at 07:32:58AM -0700, Richard Henderson wrote:
> On 5/11/22 05:05, Stafford Horne wrote:
> > +static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
> > + const TranslationBlock *tb)
> > +{
> > +Open
| 2 +-
> tcg/tcg-internal.h| 2 +-
> 20 files changed, 20 insertions(+), 20 deletions(-)
I looked at this for the OpenRISC changes, but the whole patch looks ok to me.
Reviewed-by: Stafford Horne
. This was the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.
Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.
Reported-by: Jason A. Donenfeld
Signed-off-by: Stafford Horne
---
target/openrisc
On Wed, May 04, 2022 at 01:10:04PM +0200, Jason A. Donenfeld wrote:
> On Tue, May 3, 2022 at 10:22 PM Stafford Horne wrote:
> >
> > On Tue, May 03, 2022 at 11:45:33AM +0200, Jason A. Donenfeld wrote:
> > > This appears to be a copy and paste error. The UART size was used
&
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