On Tue, Jan 2, 2018 at 11:12 PM, Richard Henderson
wrote:
>> +case CSR_MISA: {
>> +if (!(val_to_write & (1L << ('F' - 'A' {
>> +val_to_write &= ~(1L << ('D' - 'A'));
>> +}
>> +
>> +/* allow MAFDC bits in MISA to be modified */
>> +target_ulong ma
On Tue, Jul 25, 2017 at 9:37 AM, Bruce Hoult wrote:
> Do you have any good estimates for how much of the execution time is
> typically spent in instruction decode?
>
> RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing something
> right!
>
> (I suspect it's probably mostly the lack
