[Qemu-devel] [QEMU-PPC] [PATCH V4] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-08-26 Thread Suraj Jitindar Singh
then used to retrieve this information and define it for POWER8 and POWER9. Other processors will default to 0 and the charateristic won't be added. Signed-off-by: Suraj Jitindar Singh --- V1 -> V2: - Take into account that the core may be operating in split core mode meaning a single core

[Qemu-devel] [QEMU] crypto/random: Fall back to /dev/random when getrandom returns EAGAIN

2019-07-17 Thread Suraj Jitindar Singh
Hi, I'm trying to use qemu inside a a guest, however since there isn't enough entropy for the rng getrandom() blocks. This means I am unable to even get output from 'qemu --help' for example. This is annoying at best. Thinking about ways to work around this obviously the major one is to have an

Re: [Qemu-devel] [QEMU-PPC] [PATCH v3] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-07-08 Thread Suraj Jitindar Singh
On Thu, 2019-07-04 at 14:59 +1000, David Gibson wrote: > On Thu, Jul 04, 2019 at 01:41:59PM +1000, Suraj Jitindar Singh wrote: > > On Wed, 2019-07-03 at 16:12 +1000, David Gibson wrote: > > > On Mon, Jul 01, 2019 at 04:19:46PM +1000, Suraj Jitindar Singh > >

Re: [Qemu-devel] [QEMU-PPC] [PATCH v3] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-07-03 Thread Suraj Jitindar Singh
On Wed, 2019-07-03 at 16:12 +1000, David Gibson wrote: > On Mon, Jul 01, 2019 at 04:19:46PM +1000, Suraj Jitindar Singh wrote: > > The ibm,get_system_parameter rtas call is used by the guest to > > retrieve > > data relating to certain parameters of the system. The SPLPA

[Qemu-devel] [QEMU-PPC] [PATCH v3] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-07-01 Thread Suraj Jitindar Singh
tion based on the number of interrupt servers present in the device tree. Signed-off-by: Suraj Jitindar Singh --- V1 -> V2: - Take into account that the core may be operating in split core mode meaning a single core may be split into multiple subcores. V2 -> V3: - Add curly braces for single li

Re: [Qemu-devel] [QEMU-PPC] [PATCH 1/2] ppc/spapr: Add implementation of hcall H_PURR

2019-06-30 Thread Suraj Jitindar Singh
On Fri, 2019-06-28 at 19:29 +1000, David Gibson wrote: > On Mon, Jun 24, 2019 at 03:58:11PM +1000, Suraj Jitindar Singh wrote: > > The hcall H_PURR is used by a guest to read the PURR (processor > > utilisation of resources register). A guest expects that this > > register >

[Qemu-devel] [QEMU-PPC] [PATCH v2] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-06-25 Thread Suraj Jitindar Singh
tion based on the number of interrupt servers present in the device tree. Signed-off-by: Suraj Jitindar Singh --- V1 -> V2: - Take into account that the core may be operating in split core mode meaning a single core may be split into multiple subcores. --- hw/ppc/spap

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-06-25 Thread Suraj Jitindar Singh
On Mon, 2019-06-24 at 10:37 +0200, Greg Kurz wrote: > On Mon, 24 Jun 2019 11:39:21 +1000 > Suraj Jitindar Singh wrote: > > > The ibm,get_system_parameter rtas call is used by the guest to > > retrieve > > data relating to certain parameters of the system. The SPLPAR

[Qemu-devel] [QEMU-PPC] [PATCH 1/2] ppc/spapr: Add implementation of hcall H_PURR

2019-06-24 Thread Suraj Jitindar Singh
vcore. Implement a handler for the H_PURR hcall and return the purr value divided by smp_threads so that the sum of the purr deltas across the vcpus of a vcore equals the timebase delta Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 24 1 file changed

[Qemu-devel] [QEMU-PPC] [PATCH 2/2] ppc/spapr: Enable H_PURR in-kernel handling

2019-06-24 Thread Suraj Jitindar Singh
Enable in-kernel handling of the hcall H_PURR. This means that if the kernel implements an hcall handler for H_PURR, it will be used. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 3 +++ target/ppc/kvm.c | 5 + target/ppc/kvm_ppc.h | 5 + 3 files changed, 13

[Qemu-devel] [QEMU-PPC] [PATCH] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter

2019-06-23 Thread Suraj Jitindar Singh
tion based on the number of interrupt servers present in the device tree. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_rtas.c | 44 1 file changed, 44 insertions(+) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 5bc1a93271..a33d87794c 10064

Re: [Qemu-devel] [PATCH 1/2] monitor: Add dump-stack command

2019-06-20 Thread Suraj Jitindar Singh
On Wed, 2019-05-01 at 15:35 +1000, Suraj Jitindar Singh wrote: > Add a monitor command "dump-stack" to be used to dump the stack for > the > current cpu. To summarise the discussion which occured on this patch, - It looks like it's ok to duplicate this functionality as it

[Qemu-devel] [PATCH] target/ppc: Set PSSCR_EC on cpu halt to prevent spurious wakeup

2019-05-15 Thread Suraj Jitindar Singh
de. Fixes: 21c0d66a9c99 ("target/ppc: Fix support for "STOP light" states on POWER9") Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_cpu_core.c | 2 ++ hw/ppc/spapr_rtas.c | 6 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_cpu_co

Re: [Qemu-devel] [QEMU-PPC] [PATCH 02/13] target/ppc: Work [S]PURR implementation and add HV support

2019-05-06 Thread Suraj Jitindar Singh
On Mon, 2019-05-06 at 16:15 +1000, David Gibson wrote: > On Fri, May 03, 2019 at 03:53:05PM +1000, Suraj Jitindar Singh wrote: > > The Processor Utilisation of Resources Register (PURR) and Scaled > > Processor Utilisation of Resources Register (SPURR) provide an > > estimate

Re: [Qemu-devel] [QEMU-PPC] [PATCH 00/13] target/ppc: Implement KVM support under TCG

2019-05-06 Thread Suraj Jitindar Singh
On Mon, 2019-05-06 at 16:20 +1000, David Gibson wrote: > On Fri, May 03, 2019 at 03:53:03PM +1000, Suraj Jitindar Singh wrote: > > This patch series adds the necessary parts so that a tcg guest is > > able to use > > kvm facilities. That is a tcg guest can boot its own kvm g

Re: [Qemu-devel] [QEMU-PPC] [PATCH] target/ppc: Add ibm, purr and ibm, spurr device-tree properties

2019-05-06 Thread Suraj Jitindar Singh
On Mon, 2019-05-06 at 13:23 +1000, David Gibson wrote: > On Mon, May 06, 2019 at 11:48:03AM +1000, Suraj Jitindar Singh wrote: > > The ibm,purr and ibm,spurr device tree properties are used to > > indicate > > that the processor implements the Processor Utilisation of >

[Qemu-devel] [QEMU-PPC] [PATCH] target/ppc: Add ibm, purr and ibm, spurr device-tree properties

2019-05-05 Thread Suraj Jitindar Singh
processors for which the PURR and SPURR registers are generated. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2ef3ce4362..8580a8dc67 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c

[Qemu-devel] [QEMU-PPC] [PATCH 06/13] target/ppc: Enforce that the root page directory size must be at least 5

2019-05-03 Thread Suraj Jitindar Singh
According to the ISA the root page directory size of a radix tree for either process or partition scoped translation must be >= 5. Thus add this to the list of conditions checked when validating the partition table entry in validate_pate(); Signed-off-by: Suraj Jitindar Singh --- target/

[Qemu-devel] [QEMU-PPC] [PATCH 09/13] target/ppc: Implement hcall H_ENTER_NESTED

2019-05-03 Thread Suraj Jitindar Singh
the cpu state back into the guest memory. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 285 +++ include/hw/ppc/spapr.h | 3 +- target/ppc/cpu.h | 55 + target/ppc/excp_helper.c | 13 ++- 4 files changed, 353

[Qemu-devel] [QEMU-PPC] [PATCH 08/13] target/ppc: Implement hcall H_SET_PARTITION_TABLE

2019-05-03 Thread Suraj Jitindar Singh
The hcall H_SET_PARTITION_TABLE is used by a guest acting as a nested hypervisor to register the partition table entry for one of its guests with the real hypervisor. Implement this hcall for a spapr guest. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 22

[Qemu-devel] [QEMU-PPC] [PATCH 13/13] target/ppc: Enable SPAPR_CAP_NESTED_KVM_HV under tcg

2019-05-03 Thread Suraj Jitindar Singh
It is now possible to use nested kvm-hv under tcg, thus allow for it to be enabled. Note that nested kvm-hv requires that rc updates to ptes be done by software, otherwise the page tables get out of sync. So disable hardware rc updates when nested kvm-hv is enabled. Signed-off-by: Suraj Jitindar

Re: [Qemu-devel] [QEMU-PPC] [PATCH 00/13] target/ppc: Implement KVM support under TCG

2019-05-03 Thread Suraj Jitindar Singh
On Fri, 2019-05-03 at 15:53 +1000, Suraj Jitindar Singh wrote: > This patch series adds the necessary parts so that a tcg guest is > able to use > kvm facilities. That is a tcg guest can boot its own kvm guests. > > The main requirements for this were a few registers and instruc

[Qemu-devel] [QEMU-PPC] [PATCH 10/13] target/ppc: Implement hcall H_TLB_INVALIDATE

2019-05-03 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 28 include/hw/ppc/spapr.h | 3 ++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 68f3282214..a84d5e2163 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc

[Qemu-devel] [QEMU-PPC] [PATCH 11/13] target/ppc: Implement hcall H_COPY_TOFROM_GUEST

2019-05-02 Thread Suraj Jitindar Singh
can't be translated or the memory cannot be mapped then fail the access. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_hcall.c | 74 include/hw/ppc/spapr.h | 3 +- target/ppc/mmu-radix64.c | 7 ++--- target/ppc/mmu-radix64.h | 4

[Qemu-devel] [QEMU-PPC] [PATCH 05/13] target/ppc: Add privileged message send facilities

2019-05-02 Thread Suraj Jitindar Singh
FSCR and executed in privileged non-hypervisor state. Add and implement this register and instructions by reading or modifying the pending interrupt state of the cpu. Note that TCG only supports one thread per core and so we only need to worry about the cpu making the access. Signed-off-by: Suraj Jitindar S

[Qemu-devel] [QEMU-PPC] [PATCH 12/13] target/ppc: Introduce POWER9 DD2.2 cpu type

2019-05-02 Thread Suraj Jitindar Singh
Introduce a POWER9 DD2.2 cpu type with pvr 0x004E1202. A DD2.2 POWER9 cpu type is needed to enable kvm for pseries tcg guests since it means they will use the H_ENTER_NESTED hcall to run a guest rather than trying the generic entry path which will fail. Signed-off-by: Suraj Jitindar Singh

[Qemu-devel] [QEMU-PPC] [PATCH 04/13] target/ppc: Add SPR TBU40

2019-05-02 Thread Suraj Jitindar Singh
The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/ppc.c| 13 + target/ppc

[Qemu-devel] [QEMU-PPC] [PATCH 02/13] target/ppc: Work [S]PURR implementation and add HV support

2019-05-02 Thread Suraj Jitindar Singh
. Preserve this behaviour but rework the implementation to store an offset like the timebase rather than doing the calculation manually. Also allow hypervisor write access to the register along with the currently available read access. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/ppc.c

[Qemu-devel] [QEMU-PPC] [PATCH 07/13] target/ppc: Handle partition scoped radix tree translation

2019-05-02 Thread Suraj Jitindar Singh
ranslation. The process of using the radix trees to perform partition scoped translation is identical to process scoped translation, however hypervisor exceptions are generated, and thus we can reuse the radix tree traversing code. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 2 +

[Qemu-devel] [QEMU-PPC] [PATCH 00/13] target/ppc: Implement KVM support under TCG

2019-05-02 Thread Suraj Jitindar Singh
any interrupts. Suraj Jitindar Singh (13): target/ppc: Implement the VTB for HV access target/ppc: Work [S]PURR implementation and add HV support target/ppc: Add SPR ASDR target/ppc: Add SPR TBU40 target/ppc: Add privileged message send facilities target/ppc: Enforce that the root page

[Qemu-devel] [QEMU-PPC] [PATCH 01/13] target/ppc: Implement the VTB for HV access

2019-05-02 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh --- hw/ppc/ppc.c| 16 include/hw/ppc/ppc.h| 1 + linux-user/ppc/cpu_loop.c | 5 + target/ppc/cpu.h| 2 ++ target/ppc/helper.h | 2 ++ target/ppc/timebase_helper.c| 10

[Qemu-devel] [QEMU-PPC] [PATCH 03/13] target/ppc: Add SPR ASDR

2019-05-02 Thread Suraj Jitindar Singh
the ADSR, note read and write access is limited to the hypervisor. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h| 1 + target/ppc/translate_init.inc.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 19b3e1de0e

[Qemu-devel] [PATCH 2/2] ppc: Add dump-stack implementation

2019-04-30 Thread Suraj Jitindar Singh
00 gpr28: 0x0002 gpr29: 0x gpr30: 0x39ba6900 gpr31: 0x10ac85c0 sp: 0x7fffa62fdd70 Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h| 1 + target/ppc/translate.c

[Qemu-devel] [PATCH 1/2] monitor: Add dump-stack command

2019-04-30 Thread Suraj Jitindar Singh
Add a monitor command "dump-stack" to be used to dump the stack for the current cpu. Signed-off-by: Suraj Jitindar Singh --- hmp-commands.hx | 13 + hmp.h | 1 + include/qom/cpu.h | 10 ++ monitor.c | 12 qom/cpu.c

Re: [Qemu-devel] [Qemu-ppc] [PATCH for-4.0 3/3] target/ppc: Consolidate 64-bit server processor detection in a helper

2019-03-24 Thread Suraj Jitindar Singh
On Fri, 2019-03-22 at 19:03 +0100, Greg Kurz wrote: > We use PPC_SEGMENT_64B in various places to guard code that is > specific > to 64-bit server processors compliant with arch 2.x. Consolidate the > logic in a helper macro with an explicit name. Tested-by: Suraj Jitindar Singh >

Re: [Qemu-devel] [Qemu-ppc] [PATCH for-4.0 1/3] target/ppc: Fix TCG temporary leaks in gen_bcond()

2019-03-24 Thread Suraj Jitindar Singh
On Fri, 2019-03-22 at 19:03 +0100, Greg Kurz wrote: > Signed-off-by: Greg Kurz Tested-by: Suraj Jitindar Singh > --- > target/ppc/translate.c |2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 98b37

Re: [Qemu-devel] [Qemu-ppc] [PATCH for-4.0 2/3] target/ppc: Enable "decrement and test CTR" version of bcctr

2019-03-24 Thread Suraj Jitindar Singh
ER10 introduces a different behaviour. > > The existing behaviour of throwing a program interrupt is kept for > all other CPU models. > > Signed-off-by: Greg Kurz Tested-by: Suraj Jitindar Singh > --- > target/ppc/translate.c | 52 ++-- &

Re: [Qemu-devel] [Qemu-ppc] [PATCH for-4.0 0/3] target/ppc: Fix pseries.cap-ibs=workaround with TCG

2019-03-24 Thread Suraj Jitindar Singh
On Fri, 2019-03-22 at 19:03 +0100, Greg Kurz wrote: > Since recent commit 2782ad4c4102 "target/ppc/spapr: Enable > mitigations by > default for pseries-4.0 machine type", some recent distros, eg. > fedora29, > fail to boot under TCG because of a kernel panic: Good catch! I noticed this as well

[Qemu-devel] [QEMU-PPC] [PATCH] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling

2019-03-05 Thread Suraj Jitindar Singh
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest memory. Enable the in-kernel H_PAGE_INIT handler. The in-kernel handler takes half the time to complete compared to handling the H_CALL in userspace. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 3 +++ target

[Qemu-devel] [QEMU-PPC] [PATCH] target/ppc/spapr: Clear partition table entry when allocating hash table

2019-03-04 Thread Suraj Jitindar Singh
ess tables, which currently isn't supported and so couldn't have been triggered. Fixes: 00fd075e18 "target/ppc/spapr: Set LPCR:HR when using Radix mode" Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_hcall.c | 12 2 files changed, 9 ins

[Qemu-devel] [QEMU-PPC] [PATCH 2/2] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type

2019-02-28 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 708e18dcdf..b103d2677e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4314,9 +4314,9 @@ static void spapr_machine_class_init(ObjectClass

[Qemu-devel] [QEMU-PPC] [PATCH 0/2] Enable mitigations by default for pseries-4.0 machine type

2019-02-28 Thread Suraj Jitindar Singh
This series is based on the ppc-for-4.0 branch with my large-decrementer and count-cache-flush series applied. Suraj Jitindar Singh (2): target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine

[Qemu-devel] [QEMU-PPC] [PATCH 1/2] target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg

2019-02-28 Thread Suraj Jitindar Singh
these capabilities under TCG non-fatal. Instead we print a warning message to the user but still allow the guest to continue. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_caps.c | 33 - 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw

Re: [Qemu-devel] [QEMU-PPC] [PATCH 2/2] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST

2019-02-28 Thread Suraj Jitindar Singh
On Fri, 2019-03-01 at 14:19 +1100, Suraj Jitindar Singh wrote: > Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate > the requirement for a hw-assisted version of the count cache flush > workaround. > > The count cache flush workaround is a software worka

[Qemu-devel] [QEMU-PPC] [PATCH 2/2] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST

2019-02-28 Thread Suraj Jitindar Singh
being set in the characteristics returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 25 + hw/ppc/spapr_hcall.c | 3 +++ include/hw/ppc/spapr.h | 5 - target/ppc/kvm.c

[Qemu-devel] [QEMU-PPC] [PATCH 1/2] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS

2019-02-28 Thread Suraj Jitindar Singh
-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_caps.c| 21 ++--- hw/ppc/spapr_hcall.c | 5 + include/hw/ppc/spapr.h | 7 +++ target/ppc/kvm.c | 8 +++- 4 files changed, 29 insertions(+), 12 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc

[Qemu-devel] [QEMU-PPC] [PATCH v3 3/4] target/ppc: Implement large decrementer support for KVM

2019-02-28 Thread Suraj Jitindar Singh
by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: Suraj Jitindar

[Qemu-devel] [QEMU-PPC] [PATCH v3 2/4] target/ppc: Implement large decrementer support for TCG

2019-02-28 Thread Suraj Jitindar Singh
now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: Suraj Jitin

[Qemu-devel] [QEMU-PPC] [PATCH v3 4/4] target/ppc/spapr: Enable the large decrementer for pseries-4.0

2019-02-28 Thread Suraj Jitindar Singh
Enable the large decrementer by default for the pseries-4.0 machine type. It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus since they don't support the large decrementer. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 3 ++- hw/ppc/spapr_caps.c | 5 + 2

[Qemu-devel] [QEMU-PPC] [PATCH v3 1/4] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER

2019-02-28 Thread Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the availability of the large decrementer for a guest. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 17 + include/hw/ppc/spapr.h | 5 - 3 files changed, 23

Re: [Qemu-devel] [QEMU-PPC] [PATCH v2 1/4] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER

2019-02-27 Thread Suraj Jitindar Singh
On Wed, 2019-02-27 at 17:16 +1100, David Gibson wrote: > On Wed, Feb 27, 2019 at 03:30:05PM +1100, Suraj Jitindar Singh wrote: > > Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the > > availability of the large decrementer for a guest. > > > > Signed-o

[Qemu-devel] [QEMU-PPC] [PATCH] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type

2019-02-26 Thread Suraj Jitindar Singh
will have to be set to broken for tcg Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 73aba70aa9..1ef8865dc5 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4313,9 +4313,9

[Qemu-devel] [QEMU-PPC] [PATCH v2 3/4] target/ppc: Implement large decrementer support for KVM

2019-02-26 Thread Suraj Jitindar Singh
by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: Suraj Jitindar

[Qemu-devel] [QEMU-PPC] [PATCH v2 2/4] target/ppc: Implement large decrementer support for TCG

2019-02-26 Thread Suraj Jitindar Singh
now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: Suraj Jitin

[Qemu-devel] [QEMU-PPC] [PATCH v2 4/4] target/ppc/spapr: Enable the large decrementer for pseries-4.0

2019-02-26 Thread Suraj Jitindar Singh
Enable the large decrementer by default for the pseries-4.0 machine type. It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus since they don't support the large decrementer. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 3 ++- hw/ppc/spapr_caps.c | 5 + 2

[Qemu-devel] [QEMU-PPC] [PATCH v2 1/4] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER

2019-02-26 Thread Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the availability of the large decrementer for a guest. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 17 + include/hw/ppc/spapr.h | 5 - 3 files changed, 23

Re: [Qemu-devel] [QEMU-PPC] [PATCH 4/4] target/ppc/spapr: Enable the large decrementer by default on POWER9

2019-02-26 Thread Suraj Jitindar Singh
On Tue, 2019-02-26 at 14:59 +1100, David Gibson wrote: > On Tue, Feb 26, 2019 at 02:05:31PM +1100, Suraj Jitindar Singh wrote: > > Enable the large decrementer by default on POWER9 cpu models. The > > default value applied is that provided in the cpu class. > > > > Si

Re: [Qemu-devel] [QEMU-PPC] [PATCH 3/4] target/ppc: Implement large decrementer support for KVM

2019-02-26 Thread Suraj Jitindar Singh
On Tue, 2019-02-26 at 14:55 +1100, David Gibson wrote: > On Tue, Feb 26, 2019 at 02:05:30PM +1100, Suraj Jitindar Singh wrote: > > Implement support to allow KVM guests to take advantage of the > > large > > decrementer introduced on POWER9 cpus. > > > > To

Re: [Qemu-devel] [QEMU-PPC] [PATCH 2/4] target/ppc: Implement large decrementer support for TCG

2019-02-26 Thread Suraj Jitindar Singh
On Tue, 2019-02-26 at 14:53 +1100, David Gibson wrote: > On Tue, Feb 26, 2019 at 02:05:29PM +1100, Suraj Jitindar Singh wrote: > > Prior to POWER9 the decrementer was a 32-bit register which > > decremented > > with each tick of the timebase. From POWER9 onwards the decrement

Re: [Qemu-devel] [QEMU-PPC] [PATCH 1/4] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER

2019-02-25 Thread Suraj Jitindar Singh
On Tue, 2019-02-26 at 14:39 +1100, David Gibson wrote: > On Tue, Feb 26, 2019 at 02:05:28PM +1100, Suraj Jitindar Singh wrote: > > Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the > > availability and size of the large decrementer made available to &g

[Qemu-devel] [QEMU-PPC] [PATCH 2/4] target/ppc: Implement large decrementer support for TCG

2019-02-25 Thread Suraj Jitindar Singh
ned-off-by: Suraj Jitindar Singh Signed-off-by: Cédric Le Goater --- hw/ppc/ppc.c| 78 - hw/ppc/spapr.c | 8 + hw/ppc/spapr_caps.c | 38 +++- target/ppc/cpu-qom.h| 1 + tar

[Qemu-devel] [QEMU-PPC] [PATCH 3/4] target/ppc: Implement large decrementer support for KVM

2019-02-25 Thread Suraj Jitindar Singh
by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: Suraj Jitindar

[Qemu-devel] [QEMU-PPC] [PATCH 1/4] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER

2019-02-25 Thread Suraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the availability and size of the large decrementer made available to the guest. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 45

[Qemu-devel] [QEMU-PPC] [PATCH 4/4] target/ppc/spapr: Enable the large decrementer by default on POWER9

2019-02-25 Thread Suraj Jitindar Singh
Enable the large decrementer by default on POWER9 cpu models. The default value applied is that provided in the cpu class. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr_caps.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index

[Qemu-devel] [QEMU-PPC] [PATCH] target/ppc: tcg: Implement addex instruction

2018-11-14 Thread Suraj Jitindar Singh
in the xer is not modified by this instruction. For simplicity we reuse the gen_op_arith_add function and add a function argument to specify where the carry in input should come from and the carry out output be stored (note must be the same location). Signed-off-by: Suraj Jitindar Singh --- disas

[Qemu-devel] [QEMU-PPC] [PATCH V3 1/3] target/ppc: Update linux-headers for v4.19-rc7

2018-10-11 Thread Suraj Jitindar Singh
Signed-off-by: Suraj Jitindar Singh --- linux-headers/asm-powerpc/kvm.h | 1 + linux-headers/linux/kvm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h index 1b32b56a03..8c876c166e 100644 --- a/linux-headers/asm

[Qemu-devel] [QEMU-PPC] [PATCH V3 2/3] target/ppc: Add one reg id for ptcr

2018-10-11 Thread Suraj Jitindar Singh
it post migration. Add the one reg id for the ptcr. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson --- target/ppc/translate_init.inc.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c

[Qemu-devel] [QEMU-PPC] [PATCH V3 0/3] ppc/spapr: Add support for nested kvm-hv

2018-10-11 Thread Suraj Jitindar Singh
on it not changing. V2 -> V3: - The enable cap ioctl no longer takes an enable field to indicate disable/enable, but just enables the cap. So update to match this kernel change. (The cap starts out disable by default) Suraj Jitindar Singh (3): target/ppc: Update linux-headers for v4.19-rc7 target/

[Qemu-devel] [QEMU-PPC] [PATCH V3 3/3] ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV

2018-10-11 Thread Suraj Jitindar Singh
-hv=true or disabled with: -machine pseries,cap-nested-hv=false Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 32 include/hw/ppc/spapr.h | 5 - target/ppc/kvm.c | 12 target/ppc/kvm_ppc.h

[Qemu-devel] [QEMU-PPC] [PATCH V2 1/3] target/ppc: Update linux-headers for v4.19-rc7

2018-10-07 Thread Suraj Jitindar Singh
Signed-off-by: Suraj Jitindar Singh --- linux-headers/asm-powerpc/kvm.h | 1 + linux-headers/linux/kvm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h index 1b32b56a03..8c876c166e 100644 --- a/linux-headers/asm

[Qemu-devel] [QEMU-PPC] [PATCH V2 0/3] ppc/spapr: Add support for nested kvm-hv

2018-10-07 Thread Suraj Jitindar Singh
. Changes RFC -> V2: - Split header changes into separate patch - Reword error messages when enabling nested-hv with kvm Suraj Jitindar Singh (3): target/ppc: Update linux-headers for v4.19-rc7 target/ppc: Add one reg id for ptcr ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV hw/ppc/spap

[Qemu-devel] [QEMU-PPC] [PATCH V2 2/3] target/ppc: Add one reg id for ptcr

2018-10-07 Thread Suraj Jitindar Singh
it post migration. Add the one reg id for the ptcr. Signed-off-by: Suraj Jitindar Singh --- target/ppc/translate_init.inc.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 263e63cb03..487196800b

[Qemu-devel] [QEMU-PPC] [PATCH V2 3/3] ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV

2018-10-07 Thread Suraj Jitindar Singh
-hv=true or disabled with: -machine pseries,cap-nested-hv=false Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c| 32 include/hw/ppc/spapr.h | 5 - target/ppc/kvm.c | 12 target/ppc/kvm_ppc.h

[Qemu-devel] [QEMU-PPC] [RFC 2/2] ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV

2018-09-27 Thread Suraj Jitindar Singh
-hv=true or disabled with: -machine pseries,cap-netsed-hv=false Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c| 2 ++ hw/ppc/spapr_caps.c | 29 + include/hw/ppc/spapr.h| 5 - linux-headers/linux/kvm.h | 1 + target/ppc/kvm.c

[Qemu-devel] [QEMU-PPC] [RFC 0/2] ppc/spapr: Add support for nested kvm-hv

2018-09-27 Thread Suraj Jitindar Singh
linux Suraj Jitindar Singh (2): target/ppc: Add one reg id for ptcr ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c | 29 + include/hw/ppc/spapr.h | 5 - linux-headers/asm-powerpc/kvm.h

[Qemu-devel] [QEMU-PPC] [RFC 1/2] target/ppc: Add one reg id for ptcr

2018-09-27 Thread Suraj Jitindar Singh
it post migration. Add the one reg id for the ptcr. Signed-off-by: Suraj Jitindar Singh --- linux-headers/asm-powerpc/kvm.h | 1 + target/ppc/translate_init.inc.c | 10 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm

Re: [Qemu-devel] [QEMU-PPC] [PATCH] ppc/tcg: Ignore bit 6 in the eieio instruction

2018-07-01 Thread Suraj Jitindar Singh
On Fri, 2018-06-29 at 16:29 +1000, David Gibson wrote: > On Fri, Jun 29, 2018 at 04:20:24PM +1000, Suraj Jitindar Singh wrote: > > The kernel patch > > "powerpc/64s: Add support for a store forwarding barrier at kernel > > entry/exit" > > adds an eieio barrier

[Qemu-devel] [QEMU-PPC] [PATCH] ppc/tcg: Ignore bit 6 in the eieio instruction

2018-06-29 Thread Suraj Jitindar Singh
it causes an illegal instruction. To allow these kernels to run under tcg, modify the eieio instruction to ignore bit 6. Signed-off-by: Suraj Jitindar Singh --- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/transla

Re: [Qemu-devel] [PATCH] hmp-commands: use long for begin and length in dump-guest-memory

2018-06-19 Thread Suraj Jitindar Singh
On Tue, 2018-06-19 at 11:25 +0100, Dr. David Alan Gilbert wrote: > * Suraj Jitindar Singh (sjitindarsi...@gmail.com) wrote: > > The dump-guest-memory command is used to dump an area of guest > > memory > > to a file, the piece of memory is specified by a begin add

[Qemu-devel] [PATCH] [RESEND] hmp-commands: use long for begin and length in dump-guest-memory

2018-06-19 Thread Suraj Jitindar Singh
quantities to store both the begin and length values. Thus specify begin and length as long so that the entire guest memory space can be dumped. Signed-off-by: Suraj Jitindar Singh --- hmp-commands.hx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hmp-commands.hx b/hmp-command

Re: [Qemu-devel] [PATCH] hmp-commands: use long for begin and length in dump-guest-memory

2018-06-18 Thread Suraj Jitindar Singh
On Tue, 2018-06-19 at 14:48 +1000, Suraj Jitindar Singh wrote: > The dump-guest-memory command is used to dump an area of guest memory > to a file, the piece of memory is specified by a begin address and > a length. These parameters are specified as ints and thus have a > maximum &g

[Qemu-devel] [PATCH] hmp-commands: use long for begin and length in dump-guest-memory

2018-06-18 Thread Suraj Jitindar Singh
quantities to store both the begin and length values. Thus specify begin and length as long so that the entire guest memory space can be dumped. Signed-off-by: Suraj Jitindar Singh --- hmp-commands.hx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hmp-commands.hx b/hmp-command

[Qemu-devel] [QEMU-PPC] [PATCH V2 2/2] ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default

2018-06-11 Thread Suraj Jitindar Singh
In default_caps_with_cpu() we set spapr_cap_cfpc to broken for POWER8 processors and before. Since we no longer require private l1d cache on POWER8 for this cap to be set to workaround change this to default to broken for POWER7 processors and before. Signed-off-by: Suraj Jitindar Singh

[Qemu-devel] [QEMU-PPC] [PATCH V2 1/2] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache

2018-06-11 Thread Suraj Jitindar Singh
For cap_ppc_safe_cache to be set to workaround, we require both a l1d cache flush instruction and private l1d cache. On POWER8 don't require private l1d cache. This means a guest on a POWER8 machine can make use of the cache flush workarounds. Signed-off-by: Suraj Jitindar Singh --- V1 ->

Re: [Qemu-devel] [Qemu-ppc] [PATCH] target/ppc: fix tlbsync to check privilege level depending on GTSE

2018-03-14 Thread Suraj Jitindar Singh
t;target/ppc: Update tlbie to check privilege > level based on GTSE") > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> > --- > > This will have its importance when we activate the HV bit on the

[Qemu-devel] [QEMU-PPC] [PATCH V4 2/2] ppc/spapr-caps: For pseries-2.12 change spapr-cap defaults

2018-02-15 Thread Suraj Jitindar Singh
and they will have to be explicitly disabled on the command line with: -machine pseries,cap-cfpc=broken,cap-sbbc=broken Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V2 -> V3: - Set caps to workaround in the class default rather than the pseries-2.12 initialiser. --

[Qemu-devel] [QEMU-PPC] [PATCH V4 1/2] ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs

2018-02-15 Thread Suraj Jitindar Singh
helpful error message. Reported-by: Satheesh Rajendran <sathn...@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V3 -> V4: - Add this patch back from V1 to replace "ppc/spapr-caps: Convert spapr-cap-ibs to be a boolean&qu

[Qemu-devel] [QEMU-PPC] [PATCH V3 3/3] ppc/spapr-caps: For pseries-2.12 change spapr-cap defaults

2018-02-14 Thread Suraj Jitindar Singh
and they will have to be explicitly disabled on the command line with: -machine pseries,cap-cfpc=broken,cap-sbbc=broken Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V2 -> V3: - Set caps to workaround in the class default rather than the pseries-2.12 initialiser. --

[Qemu-devel] [QEMU-PPC] [PATCH V3 1/3] ppc/spapr-caps: Change migration macro to take full spapr-cap name

2018-02-14 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_caps.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 62efdaee38..e69d308560 100644 --- a/hw/ppc/spapr_caps.c +++ b/

[Qemu-devel] [QEMU-PPC] [PATCH V3 2/3] ppc/spapr-caps: Convert spapr-cap-ibs to be a boolean

2018-02-14 Thread Suraj Jitindar Singh
corresponds to the old BROKEN, that is no indirect branch serialisation. Setting this to ON corresponds to the old FIXED, that is indirect branches are serialised. Reported-by: Satheesh Rajendran <sathn...@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V2 3/3] ppc/spapr-caps: For pseries-2.12 change spapr-cap defaults

2018-02-14 Thread Suraj Jitindar Singh
On Wed, 2018-02-14 at 15:20 +0100, Greg Kurz wrote: > On Wed, 14 Feb 2018 17:51:35 +1100 > Suraj Jitindar Singh <sjitindarsi...@gmail.com> wrote: > > > For the pseries-2.12 machine type, make the spapr-caps > > SPAPR_CAP_CFPC > > and SPAPR_CAP_SBBC defaul

[Qemu-devel] [QEMU-PPC] [PATCH V2 3/3] ppc/spapr-caps: For pseries-2.12 change spapr-cap defaults

2018-02-13 Thread Suraj Jitindar Singh
and they will have to be explicitly disabled on the command line with: -machine pseries,cap-cfpc=broken,cap-sbbc=broken Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr.c | 11 ++- hw/ppc/spapr_caps.c | 10 ++ include/hw/compat.h | 2 ++ 3

[Qemu-devel] [QEMU-PPC] [PATCH V2 1/3] ppc/spapr-caps: Change migration macro to take full spapr-cap name

2018-02-13 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_caps.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 62efdaee38..e69d308560 100644 --- a/hw/ppc/spapr_caps.c +++ b/

[Qemu-devel] [QEMU-PPC] [PATCH V2 2/3] ppc/spapr-caps: Convert spapr-cap-ibs to be a boolean

2018-02-13 Thread Suraj Jitindar Singh
corresponds to the old BROKEN, that is no indirect branch serialisation. Setting this to ON corresponds to the old FIXED, that is indirect branches are serialised. Reported-by: Satheesh Rajendran <sathn...@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

[Qemu-devel] [QEMU-PPC PATCH 3/3] ppc/spapr-caps: For pseries-2.12 change spapr-cap defaults

2018-02-13 Thread Suraj Jitindar Singh
For the pseries-2.12 machine type, make the spapr-caps SPAPR_CAP_CFPC and SPAPR_CAP_SBBC default to workaround. This means the guest will be able to take advantage of these workarounds by default, so long as the host is capable. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.

[Qemu-devel] [QEMU-PPC PATCH 2/3] ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs

2018-02-13 Thread Suraj Jitindar Singh
-by: Satheesh Rajendran <sathn...@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_caps.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e69d308560..1cd73b617f 100

[Qemu-devel] [QEMU-PPC PATCH 1/3] ppc/spapr-caps: Change migration macro to take full spapr-cap name

2018-02-13 Thread Suraj Jitindar Singh
-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_caps.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 62efdaee38..e69d308560 100644 --- a/hw/ppc/spapr_caps.c +++ b/

Re: [Qemu-devel] [PATCH] spapr: add missing break in h_get_cpu_characteristics()

2018-02-01 Thread Suraj Jitindar Singh
TERISTICS" > Signed-off-by: Greg Kurz <gr...@kaod.org> Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> > --- > hw/ppc/spapr_hcall.c |1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index 4

Re: [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode

2018-02-01 Thread Suraj Jitindar Singh
On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote: > On a POWER9 processor, the first doubleword of the PTCR indicates > whether the partition uses HPT or Radix Trees translation. Use that > bit to check for radix mode on powernv QEMU machines. The above isn't quite right. On a POWER9

Re: [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9

2018-02-01 Thread Suraj Jitindar Singh
On Fri, 2018-02-02 at 13:34 +1100, Suraj Jitindar Singh wrote: > On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote: > > The Partition Table Control Register (PTCR) is a hypervisor > > privileged > > SPR. It contains the host real address of the Partition Table

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