This seems great! But does this mean that QEMU has support for a subset of
the ARM11 cores?
Also, I'm curious about ARMs position to this. I know that there has been a
licence clause that prohibits you from modelling ARM v6 CPU if you download
the ARMARM for v6 on their homepage.
Is this
Hi allI´m looking in the translate.c file in the arm part of QEMU and I´m want to understand the strategy for maintaining the cpsr bits, such as Z, N, V and C.If I remember correctly almost every instruction can change the condition codes and I guess it is quite expensive to maintain them in the
is that you see?
- Wolfgang
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wrote on 22.11.2006 22:13:01:
I?m sorry for spamming you mailing list with my duplicate posts. I
had some problems sending my mail.
/Torbjörn
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Torbjörn Andersson
Skickat
Im sorry for spamming you mailing list with my duplicate posts. I had some
problems sending my mail.
/Torbjörn
_
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Torbjörn Andersson
Skickat: den 21 november 2006 22:16
Till: qemu-devel@nongnu.org
Ämne: [Qemu-devel] ARM CPSR
Hello qemu developers!I´m using QEMU for some ARM debugging and I have som questions regardning the CPSR register. I get the feeling that the CPSR condition code bits, representing the results from the ALU, are not maintained.What I want to do is to try to verify QEMU maintains the CPSR register
Hello qemu developers!
I´m using QEMU for some ARM debugging and I have som questions regardning
the CPSR register. I get the feeling that the CPSR condition code bits,
representing the results from the ALU, are not maintained at all points. Is
the JIT in QEMU tailored in any way towards GCC
Hello qemu developers!
I´m using QEMU for some ARM debugging and I have som questions regardning
the CPSR register. I get the feeling that the CPSR condition code bits,
representing the results from the ALU, are not maintained at all points. Is
the JIT in QEMU tailored in any way towards GCC
