;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
--
1.7.3.4
Tsuneo Saito tsnsa...@gmail.com
--
Regards,
Artyom Tarasenko
solaris/sparc under qemu blog: http://tyom.blogspot.com/
Tsuneo Saito tsnsa...@gmail.com
Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.
The first patch fixes problems that are found when adding the lines
for fprs and would be better to be fixed before adding the fprs thing.
Tsuneo Saito (2):
SPARC64: fix
Fix the problem that result values are not assigned to the destination
registers.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c | 116 ++
1 files changed, 116 insertions(+), 0
This patch makes cpu_get_phys_page_debug() independent from
cpu_get_phys_page_nofault() in advance of implementing nonfaulting load.
This also modifies cpu_get_phys_page_nofault() to be compiled only on
TARGET_SPARC64 because it is not required on SPARC32.
Signed-off-by: Tsuneo Saito tsnsa
. The next 2 patches
fix the problem and the last one is for related faults other than
the TLB miss.
Tsuneo Saito (7):
SPARC64: TTE bits cleanup
SPARC64: SFSR cleanup and fix
SPARC64: introduce a convenience function for getting physical
addresses
SPARC64: split cpu_get_phys_page_debug
Introduce cpu_sparc_get_phys_page() to be used as a help for splitting
cpu_get_phys_page_debug() from cpu_get_phys_page_nofault().
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/helper.c | 20 ++--
1 files changed, 14 insertions(+), 6 deletions(-)
diff --git
Add macros for SFSR fields and use macros instead of magic numbers.
Also fix the update of the register fields on MMU faults.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/cpu.h| 22
target-sparc/helper.c | 52
(abuses?) the rw
argument of get_physical_address_data(). rw is set to 4 on nonfaulting
loads.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/cpu.h|4
target-sparc/helper.c | 29 ++---
2 files changed, 30 insertions(+), 3 deletions(-)
diff
Add macros for TTE bits and modify to use macros instead of
magic numbers.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/cpu.h|7 +++
target-sparc/helper.c | 35 +++
2 files changed, 26 insertions(+), 16 deletions(-)
diff --git
Nonfaulting loads should raise fast_data_access_MMU_miss traps as
normal loads do. It is up to the guest OS kernel that detect MMU misses
on nonfaulting load instructions and make them complete without signaling.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 36
nonfaulting loads raising MMU faults.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/helper.c |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index cb8d706..b6e62a7 100644
--- a/target-sparc/helper.c
The destination registers of SIMD signed compare instructions
(fcmp*16|32) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/helper.h|4 ++--
target-sparc
break is missing on V9 fmovdcc (%icc).
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 27c2cf9..59e91dc 100644
--- a/target-sparc
UA2007 ASI_BLK_* should be added in is_translating_asi().
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 15af27b..8b9eb9f 100644
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target
This patch series implements sparcv9 stfa/ldfa instructions that
implementations seem to be left unfinished.
This patch also adds fp_disabled exception checks on stfa/ldfa
as they are FP instructions.
v2:
* checked by checkpatch.pl.
* added UA2007 block-transfer ASIs.
* added JPS1
Support UA2007 block load ASIs for ldfa instructions.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index fe71829..b76ffb6 100644
Fixed C99 comments on block-tranfer ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 28 ++--
1 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 2a28d5f..15af27b
Support JPS1 little endian block transfer ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 4faa709..2a28d5f 100644
--- a/target
This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
with non block-load ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 15 +++
target-sparc/translate.c |2 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target
Support UA2007 block store ASIs for stfa instructions.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b76ffb6..4faa709 100644
Hi,
This patch series implements sparcv9 stfa/ldfa instructions with
non block-transfer ASIs that implementations seem to be left unfinished.
This patch also adds fp_disabled exception checks on stfa/ldfa
as they are FP instructions.
target-sparc/op_helper.c | 31
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc
This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
with non block-load ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/op_helper.c | 15 +++
target-sparc/translate.c |2 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito tsnsa...@gmail.com
---
target-sparc/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc
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