2016-06-24 1:26 GMT+08:00 Peter Maydell <peter.mayd...@linaro.org>:
> On 17 June 2016 at 03:37, Tsung-Han Lin <tsunghan...@gmail.com> wrote:
> > Hi, I made some changes to TRY TO fix the ARM semihosting issue in
> > SYS_HEAPINFO handling.
> > This problem has be
2016-06-18 14:57 GMT+09:00 Liviu Ionescu <i...@livius.net>:
>
> > On 18 Jun 2016, at 01:22, Tsung-Han Lin <tsunghan...@gmail.com> wrote:
> >
> > ... It seems like to me that the issue is the default address assumed by
> qemu, which is 0x0.
> > (since
2016-06-18 1:22 GMT+09:00 Liviu Ionescu <i...@livius.net>:
>
> > On 17 Jun 2016, at 05:37, Tsung-Han Lin <tsunghan...@gmail.com> wrote:
> >
> > Hi, I made some changes to TRY TO fix the ARM semihosting issue ...
> > This problem has been botherin
2016-06-17 17:43 GMT+09:00 Peter Maydell <peter.mayd...@linaro.org>:
> On 17 June 2016 at 03:37, Tsung-Han Lin <tsunghan...@gmail.com> wrote:
> > Hi, I made some changes to TRY TO fix the ARM semihosting issue in
> > SYS_HEAPINFO handling.
> > This problem has be
Hi, I made some changes to TRY TO fix the ARM semihosting issue in
SYS_HEAPINFO handling.
This problem has been bothering me for quite a while.
A new global variable 'main_ram_base' is added while a new memory
API, memory_region_add_subregion_main, is also provided to let
SoC/board creator to
2016-05-14 19:08 GMT+09:00 Peter Maydell :
>
>
> The ARM ARM defines that SP_EL1 is accessible only from
> EL2 or higher via the system-register instructions, and
> SP_EL2 only from EL3 or higher (see table C5-7 on page
> C5-288 of the v8 ARM ARM DDI0487A.h, or the
Fix the access rights of SP_EL2 and SP_EL1, which should be able to be
accessed from EL2 and EL1 respectively.
Signed-off-by: Tsung-Han Lin <tsunghan...@gmail.com>
---
target-arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/targ