Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

2020-10-15 Thread Victor Kamensky (kamensky)
From: Khem Raj Sent: Wednesday, October 14, 2020 1:53 PM To: Victor Kamensky (kamensky) Cc: Philippe Mathieu-Daudé; Richard Purdie; qemu-devel@nongnu.org; Aleksandar Rikalo; Aleksandar Markovic; Aurelien Jarno; Richard Henderson Subject: Re: [RFC PATCH 0/3] target/mips: Make

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

2020-10-14 Thread Victor Kamensky (kamensky)
naws.com/downloads-mips/documents/MD00419-2B-34Kf-DTS-01.20.pdf From: Philippe Mathieu-Daudé on behalf of Philippe Mathieu-Daudé Sent: Wednesday, October 14, 2020 7:53 AM To: Richard Purdie; Victor Kamensky (kamensky); qemu-devel@nongnu.org Cc: Aleksandar Rikalo; Khem Raj; Aleksandar Markovic;

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

2020-10-13 Thread Victor Kamensky (kamensky)
Hi Richard, Please forgive my cumbersome mailing agent at work. Please look inline for 'victor>' From: Richard Henderson Sent: Tuesday, October 13, 2020 7:22 PM To: Philippe Mathieu-Daudé; qemu-devel@nongnu.org; Victor Kamensky (kamensky) Cc: Aleksan

Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

2020-10-13 Thread Victor Kamensky (kamensky)
From: Philippe Mathieu-Daudé on behalf of Philippe Mathieu-Daudé Sent: Tuesday, October 13, 2020 6:25 AM To: qemu-devel@nongnu.org; Victor Kamensky (kamensky) Cc: Khem Raj; Richard Henderson; Aleksandar Rikalo; Aleksandar Markovic; Jiaxun Yang; Aurelien Jarno; Richard

[PATCH 1/1] mips: add 34Kf-64tlb fictitious cpu type like 34Kf but with 64 TLBs

2020-10-12 Thread Victor Kamensky
in the wild but given performance gains it seems to be justified. Signed-off-by: Victor Kamensky --- target/mips/translate_init.c.inc | 55 1 file changed, 55 insertions(+) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 637caccd89

[PATCH 0/1] mips: add 34Kf-64tlb fictitious cpu type like 34Kf but with 64 TLBs

2020-10-12 Thread Victor Kamensky
-models-for-mips-hosts [2] https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 [3] https://lists.openembedded.org/g/openembedded-core/message/143099 Victor Kamensky (1): mips: add 34Kf-64tlb fictitious cpu type like 34Kf but with 64 TLBs target/mips/translate_init.c.inc | 55

[Qemu-devel] [PATCH] arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT

2018-03-20 Thread Victor Kamensky
ell <peter.mayd...@linaro.org> Signed-off-by: Victor Kamensky <kamen...@cisco.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-23 Thread Victor Kamensky
On 23 January 2014 02:23, Peter Maydell peter.mayd...@linaro.org wrote: On 23 January 2014 00:22, Victor Kamensky victor.kamen...@linaro.org wrote: Peter, could I please ask you a favor. Could you please stop deleting pieces of your and my previous responses when you reply. No, sorry

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-23 Thread Victor Kamensky
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote: On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote: In [1] I wrote I don't see why you so attached to desire to describe data part of memory transaction as just one of int types. If we are talking

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-23 Thread Victor Kamensky
On 23 January 2014 08:25, Victor Kamensky victor.kamen...@linaro.org wrote: On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote: On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote: In [1] I wrote I don't see why you so attached to desire to describe

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-23 Thread Victor Kamensky
On 23 January 2014 12:45, Christoffer Dall christoffer.d...@linaro.org wrote: On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote: On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote: On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-23 Thread Victor Kamensky
On 23 January 2014 18:14, Christoffer Dall christoffer.d...@linaro.org wrote: On Thu, Jan 23, 2014 at 04:50:18PM -0800, Victor Kamensky wrote: On 23 January 2014 12:45, Christoffer Dall christoffer.d...@linaro.org wrote: On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-22 Thread Victor Kamensky
Hi Peter, On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote: On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote: Hi Guys, Christoffer and I had a bit heated chat :) on this subject last night. Christoffer, really appreciate your time! We did

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-22 Thread Victor Kamensky
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote: On 22 January 2014 17:19, Victor Kamensky victor.kamen...@linaro.org wrote: On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote: but the major issue here is that the data being transferred is not just

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-22 Thread Victor Kamensky
On 22 January 2014 12:02, Peter Maydell peter.mayd...@linaro.org wrote: On 22 January 2014 19:29, Victor Kamensky victor.kamen...@linaro.org wrote: On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote: This just isn't how real buses work. There is no address + 1, address + 2

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-22 Thread Victor Kamensky
, it will make your response email bigger, but I am very confused otherwise. On 22 January 2014 15:18, Peter Maydell peter.mayd...@linaro.org wrote: On 22 January 2014 22:47, Victor Kamensky victor.kamen...@linaro.org wrote: You deleted my example, but I need it again: Consider the following ARM code

Re: [Qemu-devel] [Qemu-ppc] KVM and variable-endianness guest CPUs

2014-01-22 Thread Victor Kamensky
Hi Alex, Sorry, for delayed reply, I was focusing on discussion with Peter. Hope you and other folks may get something out of it :). Please see responses inline On 22 January 2014 02:52, Alexander Graf ag...@suse.de wrote: On 22.01.2014, at 08:26, Victor Kamensky victor.kamen...@linaro.org

Re: [Qemu-devel] [Qemu-ppc] KVM and variable-endianness guest CPUs

2014-01-21 Thread Victor Kamensky
On 21 January 2014 22:41, Alexander Graf ag...@suse.de wrote: Am 22.01.2014 um 07:31 schrieb Anup Patel a...@brainfault.org: On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky victor.kamen...@linaro.org wrote: Hi Guys, Christoffer and I had a bit heated chat :) on this subject last night

Re: [Qemu-devel] KVM and variable-endianness guest CPUs

2014-01-21 Thread Victor Kamensky
Hi Guys, Christoffer and I had a bit heated chat :) on this subject last night. Christoffer, really appreciate your time! We did not really reach agreement during the chat and Christoffer asked me to follow up on this thread. Here it goes. Sorry, it is very long email. I don't believe we can