Re: [PATCH 1/2] linux-user/riscv: vdso: fix call frame info in __vdso_rt_sigreturn

On 1/15/24 15:18, Richard Henderson wrote: > On 1/16/24 10:15, Vineet Gupta wrote: >> When testing gcc testsuite against QEMU v8.2 we found some additional >> failures vs. v8.1.2. >> >> | FAIL: gcc.dg/cleanup-10.c execution test >> | FAIL: gcc.dg/cleanup-11.c

[PATCH 2/2] linux-user/riscv: rebuild vdso binaries after prev fix

Signed-off-by: Vineet Gupta --- Splitting this from prev patch in case maintainers want to regenerate the vdso at their end. Or if they choose to, this can be squashed with prev change too. --- Signed-off-by: Vineet Gupta --- linux-user/riscv/vdso-32.so | Bin 2900 -> 2836 bytes linux-u

[PATCH 1/2] linux-user/riscv: vdso: fix call frame info in __vdso_rt_sigreturn

Lu Signed-off-by: Vineet Gupta --- linux-user/riscv/vdso.S | 87 ++--- 1 file changed, 4 insertions(+), 83 deletions(-) diff --git a/linux-user/riscv/vdso.S b/linux-user/riscv/vdso.S index a86d8fc488e0..20119010c11b 100644 --- a/linux-user/riscv/vdso.S +++ b/

Re: [PULL 15/21] linux-user/riscv: Add vdso

On 1/12/24 16:05, Richard Henderson wrote: So by default qemu ships the vdso binary. How can one rebuild it ? From skimming the build files it seems following ought to do it     make update-linux-vdso with a prior configure cmd like below with PATH pointing to the

Re: [PULL 15/21] linux-user/riscv: Add vdso

On 1/12/24 15:37, Vineet Gupta wrote: > Now if only I could rebuild vdso/qemu with the revert of following and > the reg size change. > 2021-07-06 468c1bb5cac9 linux-user/riscv: Add vdso   And is there  way to debug qemu internals in this regard, like a developer toggle on

Re: [PULL 15/21] linux-user/riscv: Add vdso

On 1/12/24 13:35, Richard Henderson wrote: > On 1/12/24 08:49, Vineet Gupta wrote: >> Hi Richard, Alistair >> >> On 10/30/23 14:17, Richard Henderson wrote: >>> diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso >>> new file mode

Re: [PULL 15/21] linux-user/riscv: Add vdso

Hi Richard, Alistair On 10/30/23 14:17, Richard Henderson wrote: > diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso > new file mode 100644 > index 00..2c257dbfda > --- /dev/null > +++ b/linux-user/riscv/Makefile.vdso > @@ -0,0 +1,15 @@ > +include

Re: [PATCH 1/2] riscv: zicond: make non-experimental

On 8/10/23 10:14, Alistair Francis wrote: On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta wrote: zicond is now codegen supported in both llvm and gcc. This change allows seamless enabling/testing of zicond in downstream projects. e.g. currently riscv-gnu-toolchain parses elf attributes

Re: [PATCH 2/2] riscv: zicond: make default

On 8/8/23 14:06, Daniel Henrique Barboza wrote: (CCing Alistair and other reviewers) On 8/8/23 15:17, Vineet Gupta wrote: Again this helps with better testing and something qemu has been doing with newer features anyways. Signed-off-by: Vineet Gupta --- Even if we can reach a consensus

Re: [PATCH 1/2] riscv: zicond: make non-experimental

On 8/8/23 11:29, Richard Henderson wrote: On 8/8/23 11:17, Vineet Gupta wrote: zicond is now codegen supported in both llvm and gcc. It is still not in https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Right, its been frozen since April though and with support trickling

[PATCH 2/2] riscv: zicond: make default

Again this helps with better testing and something qemu has been doing with newer features anyways. Signed-off-by: Vineet Gupta --- target/riscv/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 022bd9d01223..e6e28414b223

[PATCH 1/2] riscv: zicond: make non-experimental

Signed-off-by: Vineet Gupta --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453c8..022bd9d01223 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1816,6 +1816,7 @@ static Property riscv_cpu_

Re: [PATCH] target/riscv: fix inverted checks for ext_zb[abcs]

Hi Alistair, On 2/3/22 16:59, Alistair Francis wrote: On Fri, Feb 4, 2022 at 1:42 AM Philipp Tomsich wrote: While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] inadvertently became inverted and slipped through the initial testing (which used RV64GC_XVentanaCondOps as a

[PATCH] build: fix build failure with gcc 11.2 by disabling -fcf-protection

\ | -fno-stack-protector -m16 -Wa,-32 \ | -c QEMU/pc-bios/optionrom/linuxboot_dma.c -o linuxboot_dma.o |cc1: error: ‘-fcf-protection’ is not compatible with this target Signed-off-by: Vineet Gupta --- This might be a crude fix to the problem --- pc-bios/optionrom/Makefile | 3 +++ 1

[PATCH] target/riscv: make H-extension non-experimental

H-ext v1.0 was ratified recently as part of Privileged Spec 1.12. So move it out of experimental. [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH] target/riscv: Enable bitmanip Zb[abcs] instructions

The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta

Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci

On 10/13/21 6:49 AM, Philipp Tomsich wrote: On Wed, 13 Oct 2021 at 15:44, Vincent Palatin wrote: On Wed, Oct 13, 2021 at 3:13 PM Philipp Tomsich wrote: I had a much simpler version initially (using 3 x mask/shift/or, for 12 instructions after setup of constants), but took up the suggestion

Re: [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0

On 9/27/21 1:23 PM, Jim Wilson wrote: On Mon, Sep 27, 2021 at 1:01 PM Vineet Gupta <mailto:vine...@rivosinc.com>> wrote: So I obviously forgot to get the equivalent binutils branch, but the only rvb branch on sifive fork feels dated https://github.com/riscv-col

Re: [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0

Hi, On 9/11/21 7:00 AM, Philipp Tomsich wrote: The Zb[abcs] extensions have complete public review and are nearing ratifications. These individual extensions are one part of what was previously though of as the "BitManip" (B) extension, leaving the final details of future Zb* extensions open