efn().
Opportunistically adjust cpu->phys_bits directly in
host_cpu_adjust_phys_bits(), which matches more with the function name.
Signed-off-by: Xiaoyao Li
Reviewed-by: Igor Mammedov
Reviewed-by: Zhao Liu
---
Changes in v2:
- make host_cpu_adjust_phys_bits() return void and adjust
cpu->phys_bits
development and testing. However, they
issues they aim to address are not TDX specific and the patches are not
TDX specific.
Xiaoyao Li (9):
i386/cpu: Don't construct a all-zero entry for CPUID[0xD 0x3f]
i386/cpu: Enable fdp-excptn-only and zero-fcs-fds
i386/cpu: Add support for bits in
When CPUID_EXT_MONITOR is not set, it means no support of MONITOR/MWAIT
leaf, i.e., CPUID leaf 5.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 03376ccf3e75
The whole ECX of CPUID 0x8008 is reserved for Intel.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5bee84333089..7a4835289760 100644
--- a/target/i386/cpu.c
+++ b/target/i386
When user sets tsc-frequency explicitly, the invtsc feature is actually
migratable because the tsc-frequency is supposed to be fixed during the
migration.
See commit d99569d9d856 ("kvm: Allow invtsc migration if tsc-khz
is set explicitly") for referrence.
Signed-off-by: Xiaoyao Li
-
Currently, QEMU always constructs a all-zero CPUID entry for
CPUID[0xD 0x3f].
It's meaningless to construct such a leaf as the end of leaf 0xD. Rework
the logic of how subleaves of 0xD are constructed to get rid of such
all-zero value of subleaf 0x3f.
Signed-off-by: Xiaoyao Li
---
target
When times == 1, the CPUID leaf 2 is not stateful.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index c168ff5691df..6618259f265c 100644
--- a/target/i386/kvm/kvm.c
The AMD alias bits are reserved for Intel.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fed805e04aeb..85ce405ece80 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6118,6 +6118,11
.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7a4835289760..fed805e04aeb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6863,12 +6863,16 @@ void cpu_x86_cpuid
KVM started to report the support of bit 0-5 since commit eefe5e668209
("Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace")
Allow them to be exposed to guest in QEMU.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
.
Also define the bit field MACROs so that named cpu models can add it as
well in the future.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 85ef7452c04e
On 8/13/2024 10:51 PM, Xiaoyao Li wrote:
On 8/13/2024 5:27 PM, Igor Mammedov wrote:
On Mon, 12 Aug 2024 23:31:45 -0400
Xiaoyao Li wrote:
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level
On 8/13/2024 5:27 PM, Igor Mammedov wrote:
On Mon, 12 Aug 2024 23:31:45 -0400
Xiaoyao Li wrote:
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest, e.g., -smp
e_cpuid_0x1f and x86_has_extended_topo() to check if it needs
to enable cpuid leaf 0x1f for the guest.
[1]
https://lore.kernel.org/qemu-devel/20240724075226.212882-1-manish.mis...@nutanix.com/
Signed-off-by: Xiaoyao Li
---
changes in v2:
- Add more details in commit message;
- introduce a separate function x8
On 8/8/2024 10:46 PM, Zhao Liu wrote:
On Thu, Aug 08, 2024 at 09:59:07PM +0800, Xiaoyao Li wrote:
Date: Thu, 8 Aug 2024 21:59:07 +0800
From: Xiaoyao Li
Subject: Re: [PATCH] i386/cpu: Introduce enable_cpuid_0x1f to force
exposing CPUID 0x1f
On 8/8/2024 6:09 PM, Zhao Liu wrote:
Hi Xiaoyao
On 8/8/2024 5:29 PM, Igor Mammedov wrote:
On Fri, 2 Aug 2024 03:24:26 -0400
Xiaoyao Li wrote:
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest.
above
On 8/8/2024 6:09 PM, Zhao Liu wrote:
Hi Xiaoyao,
Patch is generally fine for me. Just a few nits:
On Fri, Aug 02, 2024 at 03:24:26AM -0400, Xiaoyao Li wrote:
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index dff49fce1154..b63bce2f4c82 100644
--- a/include/hw/i386
On 8/2/2024 12:46 AM, Manish wrote:
On 01/08/24 8:41 pm, Xiaoyao Li wrote:
!---|
CAUTION: External Email
|---!
On 8/1/2024 6:25 PM, Igor Mammedov wrote:
On Thu, 1
eaf 0x1f is v2 extended topology enumration
leaf.
[1]
https://lore.kernel.org/qemu-devel/21ca5c19-677b-4fac-84d4-72413577f...@nutanix.com/
Signed-off-by: Xiaoyao Li
---
include/hw/i386/topology.h | 9 -
target/i386/cpu.c | 18 --
target/i386/cpu.h |
On 8/1/2024 6:25 PM, Igor Mammedov wrote:
On Thu, 1 Aug 2024 15:36:10 +0530
Manish wrote:
On 31/07/24 9:01 pm, Xiaoyao Li wrote:
!---|
CAUTION: External Email
On 7/31/2024 4:49 PM, John Levon wrote:
On Wed, Jul 31, 2024 at 03:02:15PM +0800, Xiaoyao Li wrote:
Windows does not expect 0x1f to be present for any CPU model. But if it
is exposed to the guest, it expects non-zero values.
Please fix Windows!
A ticket has been filed with MSFT, we are
On 7/24/2024 6:29 PM, Manish wrote:
Thanks Igor
On 24/07/24 2:30 pm, Igor Mammedov wrote:
!---|
CAUTION: External Email
|---!
On Wed, 24 Jul 2024 07:52:26 +
"
On 7/23/2024 10:26 PM, Zhao Liu wrote:
(+Xiaoyao, whose TDX work may also be related with this.)
I have a similar patch for TDX because TDX requires CPUID leaf 0x1f to
configure topology as a must.
(I haven't post to QEMU community yet. I'm not sure how people want to
proceed, refine this p
off-by: Xiaoyao Li
---
target/i386/host-cpu.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c
index 8b8bf5afeccf..b109c1a2221f 100644
--- a/target/i386/host-cpu.c
+++ b/target/i386/host-cpu.c
@@ -75,17 +75,7 @@ b
On 7/4/2024 8:34 AM, Michael Roth wrote:
On Tue, Jul 02, 2024 at 11:07:18AM +0800, Xiaoyao Li wrote:
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
SEV-SNP firmware allows a special guest page to be populated with a
table of guest CPUID values so that they can be validated
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior with Intel.
Signed-off-by: EwanHai
---
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
SEV-SNP firmware allows a special guest page to be populated with a
table of guest CPUID values so that they can be validated through
firmware before being loaded into encrypted guest memory where they can
be used in place of hypervis
ust it based on vendor in kvm_arch_get_supported_cpuid()
is better than in x86_cpu_get_supported_feature_word(). Otherwise
kvm_arch_get_supported_cpuid() still returns "risky" value for Intel VMs.
Suggested-by: Xiaoyao Li
Cc: John Allen
Signed-off-by: Paolo Bonzini
---
target/i386/c
D,
and bits from AMD should be dropped when configuring the guest for
an Intel model.
Cc: Xiaoyao Li
Cc: John Allen
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 3 +--
target/i386/cpu.c | 13 ++---
target/i386/kvm/kvm-cpu.c | 2 +-
3 files changed, 8 inserti
On 6/24/2024 11:01 PM, Daniel P. Berrangé wrote:
On Fri, Jun 14, 2024 at 08:49:57AM +0100, Daniel P. Berrangé wrote:
On Fri, Jun 14, 2024 at 09:04:33AM +0800, Xiaoyao Li wrote:
On 6/13/2024 4:35 PM, Duan, Zhenzhong wrote:
-Original Message-
From: Li, Xiaoyao
Subject: Re: [PATCH v5
On 6/14/2024 4:48 PM, Gupta, Pankaj wrote:
On 6/14/2024 10:34 AM, Xiaoyao Li wrote:
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
When guest_memfd is enabled, the BIOS is generally part of the initial
encrypted guest image and will be accessed as private guest memory. Add
the
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
Current SNP guest kernels will attempt to access these regions with
with C-bit set, so guest_memfd is needed to handle that. Otherwise,
kvm_convert_memory() will fail when the guest kernel tries to access it
and QEMU attempts to call
On 5/30/2024 7:16 PM, Pankaj Gupta wrote:
From: Michael Roth
When guest_memfd is enabled, the BIOS is generally part of the initial
encrypted guest image and will be accessed as private guest memory. Add
the necessary changes to set up the associated RAM region with a
guest_memfd backend to all
libvirt
TDX patches.
On Thu, Feb 29, 2024 at 01:36:46AM -0500, Xiaoyao Li wrote:
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it
disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise
On 6/13/2024 4:26 PM, Duan, Zhenzhong wrote:
+ *
+ * It also has side effect to enable unsupported bits, e.g., the
+ * bits of "fixed0" type while present natively. It's safe because
+ * the unsupported bits will be masked off by .fixed0 later.
+ */
+ *ret |= host_cpuid_reg
On 6/8/2024 4:34 PM, Paolo Bonzini wrote:
From: John Allen
Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to
be exposed to guests to allow them to handle machine check exceptions on AMD
hosts.
v2:
- Add "succor" feature word.
- Add case to kvm_arch_get_s
On 5/31/2024 5:27 PM, Duan, Zhenzhong wrote:
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
Due to the fact that Intel-PT virtualization support has been broken in
QEMU since Sapphire Rapids generation[1], below warning is triggered when
luanching TD guest:
warning: host doesn't support requ
On 5/31/2024 4:47 PM, Duan, Zhenzhong wrote:
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
According to Chapter "CPUID Virtualization" in TDX module spec, CPUID
bits of TD can be classified into 6 types:
1 | As
On 6/6/2024 6:45 PM, Daniel P. Berrangé wrote:
Copying Zhenzhong Duan as my point relates to the proposed libvirt
TDX patches.
On Thu, Feb 29, 2024 at 01:36:46AM -0500, Xiaoyao Li wrote:
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE
On 6/7/2024 3:46 PM, Zhao Liu wrote:
Hi Philippe,
On Fri, Jun 07, 2024 at 08:17:36AM +0200, Philippe Mathieu-Daudé wrote:
Date: Fri, 7 Jun 2024 08:17:36 +0200
From: Philippe Mathieu-Daudé
Subject: Re: [PATCH] i386/apic: Add hint on boot failure because of
disabling x2APIC
On 6/6/24 16:08, Z
On 6/6/2024 6:44 AM, Paolo Bonzini wrote:
There can be other confidential computing classes that are not derived
from sev-common. Avoid aborting when encountering them.
I hit it today when rebasing TDX patches to latest QEMU master, which
has the SEV-SNP series merged. (I didn't get time to r
izefn(), and this patch merges host_cpu_enable_cpu_pm()
into kvm_cpu_realizefn().
Fixes: f5cc5a5c1686 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass")
Fixes: 662175b91ff2 ("i386: reorder call to cpu_exec_realizefn")
Signed-off-by: Zide Chen
Reviewed-by: Xiaoyao Li
---
V3:
On 6/4/2024 5:43 PM, Zhao Liu wrote:
Hi Chuang,
On Mon, Jun 03, 2024 at 04:36:41PM +0800, Chuang Xu wrote:
Date: Mon, 3 Jun 2024 16:36:41 +0800
From: Chuang Xu
Subject: [PATCH v2] i386/cpu: fixup number of addressable IDs for processor
cores in the physical package
X-Mailer: git-send-email
On 5/13/2024 8:33 PM, Daniel P. Berrangé wrote:
Validate that it is possible to pass 'parameter=1' for any SMP topology
parameter, since unsupported parameters are implicitly considered to
always have a value of 1.
Signed-off-by: Daniel P. Berrangé
---
tests/unit/test-smp-parse.c | 8
On 4/26/2024 6:07 PM, Zhao Liu wrote:
Update the comment to match the X86ConfidentialGuestClass
implementation.
Suggested-by: Xiaoyao Li
I think it should be "Reported-by"
Signed-off-by: Zhao Liu
---
target/i386/confidential-guest.h | 2 +-
1 file changed, 1 insertion(+),
On 4/25/2024 6:29 PM, Zhao Liu wrote:
On Thu, Apr 25, 2024 at 04:40:10PM +0800, Xiaoyao Li wrote:
Date: Thu, 25 Apr 2024 16:40:10 +0800
From: Xiaoyao Li
Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
feature name
On 4/25/2024 3:17 PM, Zhao Liu wrote:
Hi Xiaoyao,
On
On 4/25/2024 3:17 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Apr 24, 2024 at 11:57:11PM +0800, Xiaoyao Li wrote:
Date: Wed, 24 Apr 2024 23:57:11 +0800
From: Xiaoyao Li
Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
feature name
On 3/29/2024 6:19 PM, Zhao Liu wrote
On 3/29/2024 6:19 PM, Zhao Liu wrote:
From: Zhao Liu
Hi list,
This series is based on Paolo's guest_phys_bits patchset [1].
Currently, the old and new kvmclocks have the same feature name
"kvmclock" in FeatureWordInfo[FEAT_KVM].
When I tried to dig into the history of this unusual naming and
On 3/29/2024 6:19 PM, Zhao Liu wrote:
From: Zhao Liu
These 2 MSRs have been already defined in the kvm_para header
(standard-headers/asm-x86/kvm_para.h).
Remove QEMU local definitions to avoid duplication.
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 3
On 3/29/2024 6:19 PM, Zhao Liu wrote:
From: Zhao Liu
Add feature definiations for KVM_CPUID_FEATURES in CPUID (
CPUID[4000_0001].EAX and CPUID[4000_0001].EDX), to get rid of lots of
offset calculations.
Signed-off-by: Zhao Liu
---
hw/i386/kvm/clock.c | 5 ++---
target/i386/cpu.h | 2
On 4/23/2024 11:09 PM, Paolo Bonzini wrote:
+
+/**
+ * x86_confidential_guest_kvm_type:
+ *
+ * Calls #X86ConfidentialGuestClass.unplug callback of @plug_handler.
the comment needs to be updated:
Calls #X86ConfidentialGuestClass.kvm_type() callback
+ */
+static inline int x86_confidential_gu
just a cleanup, so keep the function static.
Signed-off-by: Sean Christopherson
Signed-off-by: Xiaoyao Li
Message-ID: <20240229063726.610065-23-xiaoyao...@intel.com>
Reviewed-by: Xiaoyao Li
Signed-off-by: Paolo Bonzini
---
target/i386/kvm/kvm.c
On 4/16/2024 4:32 PM, Chenyi Qiang wrote:
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
Current KVM doesn't support PMU for TD guest. It returns error if TD is
created with PMU bit being set in attributes.
Disable PMU for TD guest on QEMU side.
Signed-off-by: Xiaoyao Li
---
target/i38
On 4/3/2024 11:12 PM, Igor Mammedov wrote:
On Wed, 3 Apr 2024 10:59:53 -0400
Xiaoyao Li wrote:
A value 1 of PCAT_COMPAT (bit 0) of MADT.Flags indicates that the system
also has a PC-AT-compatible dual-8259 setup, i.e., the PIC.
When PIC is not enabled (pic=off) for x86 machine, the
: Xiaoyao Li
---
changes in v2:
- Clarify more in commit message;
---
hw/i386/acpi-common.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 20f19269da40..0cc2919bb851 100644
--- a/hw/i386/acpi-common.c
+++ b/hw/i386/acpi-common.c
On 4/2/2024 10:31 PM, Michael S. Tsirkin wrote:
On Tue, Apr 02, 2024 at 09:18:44PM +0800, Xiaoyao Li wrote:
On 4/2/2024 6:02 PM, Michael S. Tsirkin wrote:
On Tue, Apr 02, 2024 at 04:25:16AM -0400, Xiaoyao Li wrote:
Set MADT.FLAGS[bit 0].PCAT_COMPAT based on x86ms->pic.
Signed-off-by: Xiao
On 4/2/2024 6:02 PM, Michael S. Tsirkin wrote:
On Tue, Apr 02, 2024 at 04:25:16AM -0400, Xiaoyao Li wrote:
Set MADT.FLAGS[bit 0].PCAT_COMPAT based on x86ms->pic.
Signed-off-by: Xiaoyao Li
Please include more info in the commit log:
what is the behaviour you observe, why it is wrong,
Set MADT.FLAGS[bit 0].PCAT_COMPAT based on x86ms->pic.
Signed-off-by: Xiaoyao Li
---
hw/i386/acpi-common.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 20f19269da40..0cc2919bb851 100644
--- a/hw/i386/acpi-commo
just a cleanup, so keep the function static.
Signed-off-by: Sean Christopherson
Signed-off-by: Xiaoyao Li
Message-ID: <20240229063726.610065-23-xiaoyao...@intel.com>
[Unify error reporting, rename function. - Paolo]
Signed-off-by: Paolo Bonzini
---
target/i386/kvm/kvm.c
On 3/21/2024 2:12 AM, Isaku Yamahata wrote:
On Wed, Mar 20, 2024 at 03:39:44AM -0500,
Michael Roth wrote:
TODO: make this SNP-specific if TDX disables legacy ROMs in general
TDX disables pc.rom, not disable isa-bios. IIRC, TDX doesn't need pc pflash.
Not TDX doesn't need pc pflash, but TDX
viewed-by: Xiaoyao Li
---
v4->v5:
- move here all non-KVM parts
- add compat property and support for special value "-1" (accelerator
defines value)
target/i386/cpu.h | 1 +
hw/i386/pc.c | 4 +++-
target/i386/cpu.c | 22 ++
3 files changed, 26 insert
On 3/23/2024 2:11 AM, Paolo Bonzini wrote:
So far, KVM has allowed KVM_GET/SET_* ioctls to execute even if the
guest state is encrypted, in which case they do nothing. For the new
API using VM types, instead, the ioctls will fail which is a safer and
more robust approach.
The new API will be th
On 3/23/2024 2:11 AM, Paolo Bonzini wrote:
From: Xiaoyao Li
KVM side leaves the memory to shared by default, while may incur the
/s/while/which/
fix typo from myself.
overhead of paging conversion on the first visit of each page. Because
the expectation is that page is likely to private
original shared
memory can be discarded via ram_block_discard_range(). Note, shared
memory can be discarded only when it's not back'ed by hugetlb because
hugetlb is supposed to be pre-allocated and no need for discarding.
Signed-off-by: Chao Peng
Co-developed-by: Xiaoyao Li
Sig
future in order to suppor migration).
From that point, skip reading registers so that cpu->vcpu_dirty is
never true: if it ever becomes true, kvm_arch_put_registers() will
fail miserably.
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
Reviewed-by: Xiaoyao Li
On 3/19/2024 9:59 PM, Paolo Bonzini wrote:
Introduce a common superclass for x86 confidential guest implementations.
It will extend ConfidentialGuestSupportClass with a method that provides
the VM type to be passed to KVM_CREATE_VM.
Signed-off-by: Paolo Bonzini
Reviewed-by: Xiaoyao Li
On 3/19/2024 9:59 PM, Paolo Bonzini wrote:
From: Xiaoyao Li
KVM is introducing a new API to create confidential guests, which
will be used by TDX and SEV-SNP but is also available for SEV and
SEV-ES. The API uses the VM type argument to KVM_CREATE_VM to
identify which confidential computing
On 3/21/2024 1:08 AM, Paolo Bonzini wrote:
On Wed, Mar 20, 2024 at 10:59 AM Paolo Bonzini wrote:
I will now focus on reviewing patches 6-20. This way we can prepare a
common tree for SEV_INIT2/SNP/TDX, for both vendors to build upon.
Ok, the attachment is the delta that I have. The only majo
On 3/19/2024 10:14 AM, Wang, Lei wrote:
On 2/29/2024 14:36, Xiaoyao Li wrote:
From: Chao Peng
When geeting KVM_EXIT_MEMORY_FAULT exit, it indicates userspace needs to
do the memory conversion on the RAMBlock to turn the memory into desired
attribute, i.e., private/shared.
Currently only
On 3/20/2024 4:39 PM, Michael Roth wrote:
TODO: squash into "kvm: handle KVM_EXIT_MEMORY_FAULT"
qemu_host_page_size has been superseded by qemu_real_host_page_size()
in newer QEMU, so update the patch accordingly.
I found it today as well when rebase to qemu v9.0.0-rc0.
Fix it locally, will s
On 3/19/2024 10:03 AM, Wang, Lei wrote:
On 2/29/2024 14:36, Xiaoyao Li wrote:> Introduce the helper functions to set
the attributes of a range of
memory to private or shared.
This is necessary to notify KVM the private/shared attribute of each gpa
range. KVM needs the information to dec
On 3/20/2024 5:37 PM, David Hildenbrand wrote:
On 20.03.24 09:39, Michael Roth wrote:
From: Xiaoyao Li
When memory page is converted from private to shared, the original
private memory is back'ed by guest_memfd. Introduce
ram_block_discard_guest_memfd_range() for discarding memo
gt;host_phys_bits && cpu->host_phys_bits_limit &&
cpu->guest_phys_bits > cpu->host_phys_bits_limt)
{
}
Simpler, we can guard with cpu->phys_bits like below, because
cpu->host_phys_bits_limit is used to guard cpu->phys_bits in
host_cpu_realizefn()
if (cpu-
On 3/19/2024 11:08 PM, Pawan Gupta wrote:
On Tue, Mar 19, 2024 at 12:22:08PM +0800, Xiaoyao Li wrote:
On 3/13/2024 10:53 PM, Pawan Gupta wrote:
Register File Data Sampling (RFDS) is a CPU side-channel vulnerability
that may expose stale register value. CPUs that set RFDS_NO bit in MSR
On 3/13/2024 10:53 PM, Pawan Gupta wrote:
Register File Data Sampling (RFDS) is a CPU side-channel vulnerability
that may expose stale register value. CPUs that set RFDS_NO bit in MSR
IA32_ARCH_CAPABILITIES indicate that they are not vulnerable to RFDS.
Similarly, RFDS_CLEAR indicates that CPU is
On 3/19/2024 5:51 AM, Paolo Bonzini wrote:
On Thu, Feb 29, 2024 at 7:01 AM Xiaoyao Li wrote:
Use confidential_guest_kvm_init() instead of calling SEV specific
sev_kvm_init(). As a bouns, it fits to future TDX when TDX implements
its own confidential_guest_support and .kvm_init().
Move the
On 3/13/2024 9:27 PM, Gerd Hoffmann wrote:
Query kvm for supported guest physical address bits, in cpuid
function 8008, eax[23:16]. Usually this is identical to host
physical address bits. With NPT or EPT being used this might be
restricted to 48 (max 4-level paging address space size) even
On 3/13/2024 11:31 PM, Daniel P. Berrangé wrote:
On Tue, Mar 12, 2024 at 03:44:32PM +0800, Xiaoyao Li wrote:
On 3/11/2024 5:27 PM, Daniel P. Berrangé wrote:
On Thu, Feb 29, 2024 at 01:37:10AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
Add property "quote-generation-socket" to
On 3/11/2024 5:27 PM, Daniel P. Berrangé wrote:
On Thu, Feb 29, 2024 at 01:37:10AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of Ge
On 3/11/2024 3:29 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 3/7/2024 9:51 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:51 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated
On 3/10/2024 9:38 PM, Zhao Liu wrote:
Hi Xiaoyao,
case 3: /* L3 cache info */
-die_offset = apicid_die_offset(&topo_info);
if (cpu->enable_l3_cache) {
+addressable_threads_width = apicid_die_offset(&topo_info);
Please get r
uot;module" level in 0x1F, decouple CPUID[0x1F] subleaf
with specific topology level.
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Besides, some nits below.
---
Changes since v7:
* Refactored the encode_topo_cpuid1f() to use traversal to search the
enco
asier to detect without touching the
topology details.
This is also in preparation for the follow-up to decouple CPUID[0x1F]
subleaf with specific topology level.
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
On 3/7/2024 9:51 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:51 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
Changes in v5:
- me
On 3/7/2024 9:56 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 3/7/2024 4:39 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 9:25 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:37 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku
On 2/27/2024 6:32 PM, Zhao Liu wrote:
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
Again as in v7, please changes to "cs->nr_co
ID to calculate this field.
[1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology
Information
Cc: Babu Moger
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
Changes since v7:
* Moved this patch after CPUID[4]'s similar change ("i386
id_core_offset(&topo_info);
And it is straightforward that it means the number of bits in x2APICID
to encode different addressable cores.
But it is not similar to addressable_threads_width, the semantic changes
per different cache level. In fact, you want something like
bi
On 3/5/2024 6:52 PM, Gerd Hoffmann wrote:
Query kvm for supported guest physical address bits, in cpuid
function 8008, eax[23:16]. Usually this is identical to host
physical address bits. With NPT or EPT being used this might be
restricted to 48 (max 4-level paging address space size) even
On 2/29/2024 4:51 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
Changes in v5:
- mention additional error information in gpa when it presents;
- refin
On 2/29/2024 9:28 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:40 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation S
On 3/7/2024 4:39 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 9:25 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:37 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig
On 3/5/2024 5:10 PM, Isaku Yamahata wrote:
On Thu, Feb 29, 2024 at 01:36:29AM -0500,
Xiaoyao Li wrote:
From: Chao Peng
When geeting KVM_EXIT_MEMORY_FAULT exit, it indicates userspace needs to
do the memory conversion on the RAMBlock to turn the memory into desired
attribute, i.e., private
On 3/4/2024 10:58 PM, Gerd Hoffmann wrote:
On Mon, Mar 04, 2024 at 09:54:40AM +0800, Xiaoyao Li wrote:
On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
query kvm for supported guest physical address bits using
KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
(leaf 0x8008, eax, bits
On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
query kvm for supported guest physical address bits using
KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
(leaf 0x8008, eax, bits 16-23).
Signed-off-by: Gerd Hoffmann
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 1 +
ta
On 2/29/2024 9:25 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
On 2/29/2024 4:37 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them
On 2/29/2024 4:40 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of GetQuote, it connects to the QGS so
On 2/29/2024 4:37 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef
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