AVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK;
-env->features[FEAT_XSAVE_XSS_HI] = mask >> 32;
+env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32;
}
Thanks for fixing this!
Reviewed-by: Yang Weijiang
/* Steps involved on loading and filtering CPUID data
; CPUID_EXT_XSAVE)) {
env->features[FEAT_XSAVE_XCR0_LO] = 0;
env->features[FEAT_XSAVE_XCR0_HI] = 0;
+env->features[FEAT_XSAVE_XSS_LO] = 0;
+env->features[FEAT_XSAVE_XSS_HI] = 0;
return;
}
Thanks for fixing this!
Reviewed-by: Yang Weijiang
On 9/1/2023 1:30 PM, Li, Xin3 wrote:
FRED CPU states are managed in 10 FRED MSRs, in addtion to a few existing
CPU registers and MSRs, e.g., the CR4.FRED bit.
Add the 10 new FRED MSRs to x86 CPUArchState for live migration support.
Tested-by: Shan Kang
Signed-off-by: Xin Li
---
CET QEMU series which includes this bit enabling.
Reviewed-by: Yang Weijiang
.
v1 link:
https://lore.kernel.org/all/20230421041227.90915-1-weijiang.y...@intel.com/
Yang Weijiang (4):
target/i386: Enable XSAVES support for CET states
target/i386: Add CET MSRs access interface
target/i386: Add CET states to vmstate
target/i386: Advertise CET related flags in feature
that KVM can enumerate the features properly.
CET feature is only available on platforms with IA32_VMX_BASIC[bit 56]
set, otherwise, CET features are disabled in KVM.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
):ECX[7] and EDX[20]
respectively, two featues share the same state bits in XSS,so
if either of the features is enabled, set CET_U and CET_S bits
together.
Opportunistically fix the array format issue.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 45
pointer
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 18 +
target/i386/kvm/kvm.c | 59 +++
2 files changed, 77 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 06855e0926..ef1f3d6138 100644
--- a/target/i386/cpu.h
Add CET states in vmstate if the feature is enabled.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 28
1 file changed, 28 insertions(+)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index c7ac8084b2..6d42f6dc7e 100644
--- a/target/i386
On 6/13/2023 9:19 PM, Xiaoyao Li wrote:
CPUID leaf 7 was grouped together with SGX leaf 0x12 by commit
b9edbadefb9e ("i386: Propagate SGX CPUID sub-leafs to KVM") by mistake.
SGX leaf 0x12 has its specific logic to check if subleaf (starting from 2)
is valid or not by checking the bit 0:3 of
On 6/13/2023 9:19 PM, Xiaoyao Li wrote:
No such constraint that subleaf index needs to be less than 64.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index afa97799d89a..d7e235ce35a6
On 6/13/2023 9:19 PM, Xiaoyao Li wrote:
Decrease array index cpuid_i when CPUID leaf 1F is skipped, otherwise it
will get an all zero'ed CPUID entry with leaf 0 and subleaf 0. It
conflicts with correct leaf 0.
Maybe change the commit log like this:
Exiting code misses a decrement of cpuid_i
these flags so that KVM can support the features properly.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index be86df8c1d..f11c5ce86c 100644
--- a/target/i386/cpu.c
+++ b/target/i386
Add supported CET states in vmstate for VM migration.
Other MSRs, i.e., MSR_IA32_PL{0,1,2}_SSP and MSR_IA32_INTR_SSP_TBL
are for non-supported supervisor mode shadow stack, are ignored now.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 81
MSRs, i.e., MSR_IA32_PL{0,1,2}_SSP and MSR_IA32_INTR_SSP_TBL
are for non-supported supervisor mode shadow stack, are ignored now.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 10 ++
target/i386/kvm/kvm.c | 44 +++
2 files changed, 54
These are VMM userspace enabling patches for CET virtualization.
Currently CET user mode SHSTK/IBT and kernel mode IBT are supported.
supervisor SHSTK are not supported now, so related MSRs support
are not included in this series.
Yang Weijiang (4):
target/i386: Enable XSAVES support for user
] and EDX[20]
respectively, two featues share the same bit for user mode states.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 39 +++
target/i386/cpu.h | 13 +
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/target/i386/cpu.c b
On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang wrote:
On 10/26/2022 7:57 PM, Zhong, Yang wrote:
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave
env->features[FEAT_XSAVE_XSS_HI];
+*ecx &= env->features[FEAT_XSAVE_XCR0_LO];
+*edx &= env->features[FEAT_XSAVE_XCR0_HI];
Oops, that's my fault to replace with wrong definitions, thanks for the fix!
Reviewed-by: Yang Weijiang
/* FP an
Live migration can happen when Arch LBR LBREn bit is cleared,
e.g., when migration happens after guest entered SMM mode.
In this case, we still need to migrate Arch LBR MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/kvm/kvm.c | 21 +
1 file changed, 9 insertions(+), 12
Define Arch LBR bit in XSS and save/restore structure
for XSAVE area size calculation.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 6 +-
target/i386/cpu.h | 23 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386
code and it'll be
used by Arch LBR patch too.
patch 4~5: Enable XSAVES support for Arch LBR.
patch 6~7: Enable Arch LBR live migration support.
patch 8: Advertise Arch LBR feature.
Yang Weijiang (8):
qdev-properties: Add a new macro with bitmask check for uint64_t
property
} to
FEAT_XSAVE_XCR0_{LO|HI} to differentiate clearly the feature
bits in XCR0 and those in XSS.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 104 +++---
target/i386/cpu.h | 13 +-
2 files changed, 91 insertions(+), 26 deletions(-)
diff --git
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Yang Weijiang
The Arch LBR record MSRs and control MSRs will be migrated
to destination guest if the vcpus were running with Arch
LBR active.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target/i386
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang
---
target
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
include/hw
its bitmask (0x3f).
6) Target guest LBR format matches that of host.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 40
target/i386/cpu.h | 10 ++
2 files changed, 50 insertions(+)
diff --git
mismatches MSR_ARCH_LBR_DEPTH.
In most of the cases Arch LBR is not in active status,
so check the control bit before save/restore the big
chunck of Arch LBR MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 10 +++
target/i386/kvm/kvm.c | 67
Ping...
Does this v2 meet the requirement?
On 1/30/2022 7:07 AM, Yang Weijiang wrote:
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call
On 2/9/2022 5:14 PM, Like Xu wrote:
Hi Weijiang,
On 23/1/2022 12:11 am, Yang Weijiang wrote:
KVM legacy LBR patches have been merged in kernel 5.12, this patchset
is to expose the feature to guest from the perf capability MSR. Qemu can
add LBR format in cpu option to achieve it, e.g., -cpu
the helper before uses to eliminate
a forward declaration.
base-commit: 48302d4eb628ff0bea4d7e92cbf6b726410eb4c3
Signed-off-by: Yang Weijiang
---
target/i386/kvm/kvm.c | 48 ---
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git a/target/i386/kvm
On 1/28/2022 6:55 PM, Paolo Bonzini wrote:
On 1/27/22 16:58, Yang Weijiang wrote:
@@ -135,6 +135,7 @@ static struct kvm_msr_list *kvm_feature_msrs;
#define BUS_LOCK_SLICE_TIME 10ULL /* ns */
static RateLimit bus_lock_ratelimit_ctrl;
+static int kvm_get_one_msr(X86CPU *cpu, int
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang
---
target
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
include/hw
LBR solution accelerates guest perf performace by LBR MSR
passthrough so it requires guest cpu model matches that of host's, i.e.,
only -cpu host is supported.
Change in v5:
1. This patchset is rebased on tip : 6621441db5
2. No functional change since v4.
Yang Weijiang (2):
qdev
its bitmask (0x3f).
6) Target guest LBR format matches that of host.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 40
target/i386/cpu.h | 10 ++
2 files changed, 50 insertions(+)
diff --git
On Sun, Jun 20, 2021 at 10:42:36AM +0800, Yang, Weijiang wrote:
Hi, Paolo and Eduardo,
Legacy Arch LBR patches have been merged in 5.12 kernel tree, these patches
are corresponding change from QEMU side, without these patches,legacy Arch LBR
cannot work, could you review them at your convenience
Hello, maintainers,
Could you review this patch series kindly since the legacy LBR patches
have been merged in 5.12 kernel tree?
Thanks!
On Sun, Jun 20, 2021 at 10:42:36AM +0800, Yang, Weijiang wrote:
> The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
> user-su
its bitmask (0x3f).
6) Target guest LBR format matches that of host.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 41 +
target/i386/cpu.h | 10 ++
2 files changed, 51 insertions(+)
diff
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
include/hw
Save the MSRs being used on source machine and restore them
on destination machine.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 161 ++
1 file changed, 161 insertions(+)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index
.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 18 +++
target/i386/kvm/kvm.c | 72 +++
2 files changed, 90 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 593a2d6823..a5bb049d4e 100644
--- a/target/i386/cpu.h
+++ b
CET SHSTK and IBT feature are enumerated via CPUID.(EAX=07H,ECX=0H):ECX[bit 7]
and EDX[bit 20]. CET state load/restore at vmentry/vmexit are enabled via
VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28].
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 8
1 file changed, 4
Rename XSAVE related feature-words for introducing XSAVES related
feature-words.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 24
target/i386/cpu.h | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
-by: Yang Weijiang
---
target/i386/cpu.c | 42 +-
target/i386/cpu.h | 21 +
2 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d74d68e319..bae827c8d5 100644
--- a/target/i386/cpu.c
+++ b
Currently, CPUID.(EAX=0DH,ECX=01H) doesn't enumerate features in XSS
properly, so enable the support. XCR0 bits indicate user-mode XSAVE
components, and XSS bits indicate supervisor-mode XSAVE components.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 68
to 6.0.0.
v7 patch:
https://lore.kernel.org/kvm/20210226022058.24562-1-weijiang.y...@intel.com
CET KVM patches:
https://git.kernel.org/pub/scm/virt/kvm/kvm.git/log/?h=intel
CET kernel patches:
https://lkml.kernel.org/r/20210427204315.24153-1-yu-cheng...@intel.com
Yang Weijiang (6):
target/i386
On Thu, May 06, 2021 at 06:16:47PM -0400, Eduardo Habkost wrote:
> On Fri, Feb 26, 2021 at 10:20:54AM +0800, Yang Weijiang wrote:
> > Currently, CPUID.(EAX=0DH,ECX=01H) doesn't enumerate features in
> > XSS properly, add the support here. XCR0 bits indicate user-mode XSAVE
> >
.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 18
target/i386/kvm.c | 72 +++
2 files changed, 90 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a43fb6d597..83628e823c 100644
--- a/target/i386/cpu.h
+++ b/target
Save the MSRs being used on source machine and restore them
on destination machine.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 161 ++
1 file changed, 161 insertions(+)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index
Currently, CPUID.(EAX=0DH,ECX=01H) doesn't enumerate features in
XSS properly, add the support here. XCR0 bits indicate user-mode XSAVE
components, and XSS bits indicate supervisor-mode XSAVE components.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 48
CET SHSTK and IBT feature are enumerated via CPUID.(EAX=07H,ECX=0H):ECX[bit 7]
and EDX[bit 20]. CET state load/restore at vmentry/vmexit are enabled via
VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28].
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 8
1 file changed, 4
Rename XSAVE related feature-words for introducing XSAVES related
feature-words.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 24
target/i386/cpu.h | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
:
https://lkml.kernel.org/r/20210203113421.5759-1-weijiang.y...@intel.com
CET kernel patches:
https://lkml.kernel.org/r/20210217222730.15819-1-yu-cheng...@intel.com
Yang Weijiang (6):
target/i386: Change XSAVE related feature-word names
target/i386: Enable XSS feature enumeration for CPUID
-by: Yang Weijiang
---
target/i386/cpu.c | 35 +++
target/i386/cpu.h | 23 ++-
2 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f3923988ed..ef786b920e 100644
--- a/target/i386/cpu.c
+++ b
On Sun, Jan 24, 2021 at 02:08:29PM -0700, Nathan Chancellor wrote:
> On Wed, Jan 13, 2021 at 05:04:30PM +0800, Yang Weijiang wrote:
> > QEMU option -cpu max(max_features) means "Enables all features supported by
> > the accelerator in the current host", this looks
On Wed, Jan 13, 2021 at 11:06:09AM +0100, Paolo Bonzini wrote:
> On 13/01/21 10:04, Yang Weijiang wrote:
> > QEMU option -cpu max(max_features) means "Enables all features supported by
> > the accelerator in the current host", this looks true for all the features
>
QEMU option -cpu max(max_features) means "Enables all features supported by
the accelerator in the current host", this looks true for all the features
except guest max physical address width, so add this patch to enable it.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 2
On Tue, Oct 13, 2020 at 05:08:54PM -0700, Sean Christopherson wrote:
> On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote:
> > With more components in XSS being developed on Intel platform,
> > it's necessary to clean up existing XSAVE related feature words to
> >
CET SHSTK and IBT feature are enumerated via CPUID.(EAX=07H,ECX=0H):ECX[bit 7]
and EDX[bit 20]. CET state load/restore at vmentry/vmexit are enabled via
VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28].
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 8
1 file changed, 4
Save the MSRs being used on source machine and restore them
on destination machine.
Signed-off-by: Yang Weijiang
---
target/i386/machine.c | 161 ++
1 file changed, 161 insertions(+)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index
With more components in XSS being developed on Intel platform,
it's necessary to clean up existing XSAVE related feature words to
make the name clearer. It's to prepare for adding CET related support
in following patches.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c| 60
-by: Yang Weijiang
---
target/i386/cpu.c | 18 ++
target/i386/cpu.h | 23 ++-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 38eab02b3d..5496fd68d4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
Currently, CPUID.(EAX=0DH,ECX=01H) doesn't enumerate features in
XSS properly, add the support here. XCR0 bits indicate user-mode XSAVE
components, and XSS bits indicate supervisor-mode XSAVE components.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 48
.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 18
target/i386/kvm.c | 73 +++
2 files changed, 91 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d4563fa0e8..9c0568672e 100644
--- a/target/i386/cpu.h
+++ b
=d, ECX=n), set return ECX = 1 if bit n corresponds
to a bit in MSR_IA32_XSS.
- Skip Supervisor mode xsave component when calculate User mode
xave component size in xsave_area_size() and x86_cpu_reset().
Yang Weijiang (6):
x86/cpu: Rename XSAVE related feature words.
x86/cpuid: Enable
Added interface for CET MSR_IA32_{U,S}_CET, MSR_IA32_PL{0,1,2,3}_SSP,
MSR_IA32_INTR_SSP_TBL and MSR_KVM_GUEST_SSP save/restore. Check if
corresponding CET features are available before access the MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 18 +
target/i386/kvm.c
storage size.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 38 --
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 90ffc5f3b1..3174e05482 100644
--- a/target/i386/cpu.c
12 in XSS.
CPUID(0xD,11): user mode CET state sub-leaf, reports the state size.
CPUID(0xD,12): supervisor mode CE state sub-leaf, reports the state size.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 19 ++-
1 file changed, 18 insertions(+), 1 delet
() and x86_cpu_reset().
Yang Weijiang (4):
x86/cpu: Add CET CPUID/XSAVES flags and data structures
x86/cpuid: Add XSAVES feature words and CET related state bits
x86/cpuid: Add support for XSAVES dependent feature enumeration
x86/cpu: Add user space access interface for CET MSRs
target/i386
.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e818fc712a..ed03cd1760 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP/PL1_SSP/PL2_SSP/PL3_SSP
and SSP_TABL_ADDR MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 33 -
1 file changed, 32
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f6c7bdf6fe..11dbb9bcc4
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386
in MSR_IA32_XSS.
- In CPUID.(EAX=d, ECX=n), set return ECX = 1 if bit n corresponds
to a bit in MSR_IA32_XSS.
- Skip Supervisor mode xsave component when calculate User mode
xave component size in xsave_area_size() and x86_cpu_reset().
Yang Weijiang (5):
Add CET xsaves/xrstors related macros
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP, PL3_SSP and SSP_TABL_ADDR
MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 12
calculate User mode
xave component size in xsave_area_size() and x86_cpu_reset().
Yang Weijiang (5):
Add CET xsaves/xrstors related macros and structures.
Add CET SHSTK and IBT CPUID feature-word definitions.
Add hepler functions for CPUID xsave area size calculation.
Report CPUID xsave area
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 36 +++-
1 file changed, 35
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP, PL3_SSP and SSP_TABL_ADDR
MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 12
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 36 +++-
1 file changed, 35
corresponds
to a bit in MSR_IA32_XSS.
- Skip Supervisor mode xsave component when calculate User mode
xave component size in xsave_area_size() and x86_cpu_reset().
Yang Weijiang (5):
Add CET xsaves/xrstors related macros and structures.
Add CET SHSTK and IBT CPUID feature-word definitions
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 36 +++-
1 file changed, 35
() and x86_cpu_reset().
Yang Weijiang (4):
Add CET xsaves/xrstors related macros and structures.
Add CET SHSTK and IBT CPUID feature-word definitions.
Add hepler functions for CPUID xsave area size calculation.
Report CPUID xsave area support for CET.
target/i386/cpu.c | 73
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target
On Fri, Dec 28, 2018 at 03:25:10PM +0100, Paolo Bonzini wrote:
Thanks a lot Paolo for the comments!
I'll fix the issue in next version.
> On 26/12/18 09:25, Yang Weijiang wrote:
> > @@ -1233,6 +1252,14 @@ static const ExtSaveArea x86_ext_save_areas[] = {
> >{ .feature
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Control-flow Enforcement Technology (CET) provides protection against
return/jump-oriented programming (ROP) attacks. To make kvm Guest OS
own the capability, this patch-set is required. It enables CET related
CPUID report and xsaves/xrstors support etc in qemu.
Yang Weijiang (4):
Add CET
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