Hi Cedric
Could you clarify what functional test you are referring to?
Thanks
Yubin
On Tue, Sep 16, 2025 at 11:10 PM Cédric Le Goater wrote:
> Hi,
>
> On 9/16/25 19:50, Yubin Zou wrote:
> > From: Patrick Venture
> >
> > Adds eeprom init for aspeed helper method an
driver backend
by using the `-drive`option.
Signed-off-by: Yubin Zou
---
Patrick Venture (2):
hw/arm: add eeproms to quanta-q7l1 board
hw/arm: enable eeproms for quanta-q71l
hw/arm/aspeed.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
---
base-commit
From: Patrick Venture
Tested: Quanta-q71l firmware booted to login and was populated via the
-drives for the corresponding eeproms.
Signed-off-by: Patrick Venture
---
hw/arm/aspeed.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
From: Patrick Venture
Adds eeprom init for aspeed helper method and adds 24c64 eeproms to the
quanta-q71l bmc board.
Tested: Booted quanta-q71l bmc firmware to userspace.
Signed-off-by: Patrick Venture
---
hw/arm/aspeed.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
From: Titus Rwantare
Signed-off-by: Titus Rwantare
---
hw/arm/npcm8xx.c | 3 +-
hw/pci-host/npcm_pcierc.c | 137 ++
include/hw/pci-host/npcm_pcierc.h | 22 +-
3 files changed, 160 insertions(+), 2 deletions(-)
diff --git a/hw/
From: Titus Rwantare
create a basic device to introduce the root complex registers and
respond to its mmio configuration accesses
Signed-off-by: Titus Rwantare
---
hw/pci-host/Kconfig | 4 +
hw/pci-host/meson.build | 1 +
hw/pci-host/npcm_pcierc.c | 16
From: Titus Rwantare
Signed-off-by: Titus Rwantare
---
hw/arm/Kconfig | 3 ++-
hw/arm/npcm8xx.c | 10 +-
include/hw/arm/npcm8xx.h | 2 ++
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index
2aa4b5d77864ff01e69650711e
From: Titus Rwantare
Adds the windowing registers without address translation
Signed-off-by: Titus Rwantare
---
hw/pci-host/npcm_pcierc.c | 223 +-
include/hw/pci-host/npcm_pcierc.h | 77 -
2 files changed, 297 insertions(+), 3 deletions
From: Titus Rwantare
This switches to a using a fully sized PCI memory region that's
separate from system memory. Accesses to this PCI memory region are
gated by the AXI to PCIe windows whose size and offsets are validated.
- PCIe config space is not necessarily aliased with PCIe mmio space.
From: Hao Wu
GitWatcher: ignore
Google-Bug-Id: 262946103
Google-Bug-Id: 240169286
Signed-off-by: Hao Wu
Change-Id: I77ce849af30e999ec26aeab62b7db437db28c012
---
hw/arm/Kconfig | 1 +
hw/arm/npcm7xx.c | 10 ++
include/hw/arm/npcm7xx.h | 4 +++-
3 files changed, 14 ins
faithful representation of the on-chip PCIe hardware.
Signed-off-by: Yubin Zou
---
Hao Wu (1):
hw/arm: Add PCIERC to NPCM7xx SoC
Titus Rwantare (6):
hw/pci-host: implement Nuvoton PCIE Root Complex stub
hw/pci-host: add basic Nuvoton PCIe window support
hw/arm: attach PCIe
From: Titus Rwantare
This allows MSI capable qemu devices to attach to the root complex
Signed-off-by: Titus Rwantare
---
hw/pci-host/npcm_pcierc.c | 5 +
include/hw/pci-host/npcm_pcierc.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-hos
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