[PATCH RESEND 0/6] Introduce extension implied rules

Reviewed-by: Jerry Zhang Jian -- 2.44.0

[PATCH v2] target/riscv: zvbb implies zvkb

- According to RISC-V crypto spec, Zvkb extension is a proper subset of the Zvbb extension. - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian --- target/riscv

Re: [PATCH] target/riscv: zvbb implies zvkb

Sorry, I had the bad mail client setting. Please ignore the previous email, and I will resubmit the patch. -- Jerry Jerry ZJ 於 2024年5月28日 週二 下午8:12寫道： > > *Canary Mail You've received a secure email* > jerry.zhangj...@sifive.com has sent you a secure email via Canary Mail. > Read Secure Email

[PATCH] target/riscv: zvbb implies zvkb

- According to RISC-V crypto spec, Zvkb extension is a proper subset of the Zvbb extension. - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian --- target/riscv

[PATCH] target/riscv: don't enable Zfa by default

- Zfa requires F, we should not assume all CPUs have F extension support. Signed-off-by: Jerry Zhang Jian --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..c9f11509c8 100644 --- a/target/riscv

Re: [Phishing Risk] [External] Re: [PATCH 0/3] Add a host power device

Hi Philippe, Thanks for your reply. On Tue, Sep 20, 2022 at 7:09 AM Philippe Mathieu-Daudé wrote: > > Hi Jian, > > On 19/9/22 19:21, Jian Zhang wrote: > > This patchset adds a host power device and added it into the g220a > > mahcine. The BMC have a important is to control the power of the