From: TANG Tiancheng
vmstate_riscv_cpu was missing env.stimer and env.vstimer.
Without migrating these QEMUTimer fields, active S/VS-mode
timer events are lost after snapshot or migration.
Add VMSTATE_TIMER_PTR() entries to save and restore them.
Reviewed-by: LIU Zhiwei
Reviewed-by: Daniel Hen
From: Frank Chang
Currently, the SiFive UART raises an IRQ whenever:
1. ie.txwm is enabled.
2. ie.rxwm is enabled and the Rx FIFO is not empty.
It does not check the watermark thresholds set by software. However,
since commit [1] changed the SiFive UART character printing from
synchronous t
From: Joel Stanley
The iommu Linux kernel support is now upstream. VFIO is still
downstream at this stage.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Joel Stanley
Message-ID: <20250814001452.504510-1-j...@jms.id.au>
Signed-off-by: Alistair Francis
---
docs/specs/riscv-iommu.rst | 35
From: Vladimir Isaev
opcode_at is used only in semihosting checks to match opcodes with expected
pattern.
This is not a translator and if we got following assert if page is not in TLB:
qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion
`offset == db->record_start + db->re
From: Jim Shu
When sspopchk is in the middle of TB and triggers the SW check
exception, it should update PC from gen_update_pc(). If not, RISC-V mepc
CSR will get wrong PC address which is still at the start of TB.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Message-ID: <2025092407481
From: Andrea Bolognani
Descriptors using this value have been shipped for years
by distros, so we just need to update the spec to match
reality.
Signed-off-by: Andrea Bolognani
Reviewed-by: Kashyap Chamarthy
Message-ID: <20250910121501.676219-1-abolo...@redhat.com>
Signed-off-by: Alistair Fran
From: stove
Commit 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC
writes a read-only CSR") changed the behavior of riscv_csrrw, which
would formerly be treated as read-only if the write mask were set to 0.
Fixes an exception being raised when accessing read-only vector CSRs
lik
From: Xuemei Liu
Similar to other architectures (e.g., x86_64, aarch64), utilizing THP on RISC-V
KVM requires 2MiB-aligned memory blocks.
Signed-off-by: Xuemei Liu
Reviewed-by: David Hildenbrand
Message-ID: <20250924131803656yqt9zjkfevwkinagpp...@zte.com.cn>
Signed-off-by: Alistair Francis
--
From: Jim Shu
In VU/VS mode, accessing $ssp CSR will trigger the virtual instruction
exception instead of illegal instruction exception if SSE is disabled
via xenvcfg CSRs.
This is from RISC-V CFI v1.0 spec ch2.2.4. Shadow Stack Pointer
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Mes
From: TANG Tiancheng
In QEMU's RISC-V ACLINT timer model, 'mtime' is not stored directly as a
state variable. It is computed on demand as:
mtime = rtc_r + time_delta
where:
- 'rtc_r' is the current VM virtual time (in ticks) obtained via
cpu_riscv_read_rtc_raw() from QEMU_CLOCK_VIRTUAL.
-
From: Max Chou
The Zve32x extension will be applied by the V and Zve* extensions.
Therefore we can replace the original V checking with Zve32x checking for both
the V and Zve* extensions.
Signed-off-by: Max Chou
Reviewed-by: Alistair Francis
Message-ID: <20250923090729.1887406-2-max.c...@sifiv
From: "Guo Ren (Alibaba DAMO Academy)"
Current implementation is wrong when iohgatp != bare. The RISC-V
IOMMU specification has defined that the PDT is based on GPA, not
SPA. So this patch fixes the problem, making PDT walk correctly
when the G-stage table walk is enabled.
Fixes: 0c54acb8243d ("
From: Philippe Mathieu-Daudé
Use the existing riscv_cpu_is_32bit() helper to check for 32-bit CPU.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20250924164515.51782-1-phi...@linaro.org>
Signed-off-by: Alistair Francis
---
target/
From: Jim Shu
Follow the RISC-V CFI v1.0 spec [1] to fix the exception type
when ssamoswap is disabled by xSSE.
[1] RISC-V CFI spec v1.0, ch2.7 Atomic Swap from a Shadow Stack Location
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Message-ID: <20250924074818.230010-4-jim@sifive.com
From: vhaudiquet
Three instructions were not using the endianness swap flag, which resulted in a
bug on big-endian architectures.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131
Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828
Fixes: e0a3054f18e ("target/riscv:
From: TANG Tiancheng
The current 'timecmp' field in vmstate_riscv_mtimer is insufficient to keep
timers functional after migration.
If an mtimer's entry in 'mtimer->timers' is active at the time the snapshot
is taken, it means riscv_aclint_mtimer_write_timecmp() has written to
'mtimecmp' and sch
From: Frank Chang
There's no need to call fifo8_push_all() when size is zero.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-ID: <20250911160647.5710-3-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
hw/char/sifive_uart.c | 4 +++-
1 file changed, 3 insertions(+
From: Daniel Henrique Barboza
Update OpenSBI and the pre-built opensbi32 and opensbi64 images to
version 1.7.
It has been almost an year since we last updated OpenSBI (at the time,
up to v1.5.1) and we're missing a lot of good stuff from both v1.6 and
v1.7, including SBI 3.0 and RPMI 1.0.
The c
From: Andrew Jones
The MSI table is not limited to 4k. The only constraint the table has
is that its base address must be aligned to its size, ensuring no
offsets of the table size will overrun when added to the base address
(see "8.5. MSI page tables" of the AIA spec).
Fixes: 0c54acb8243d ("hw/
From: Alistair Francis
The following changes since commit 29b77c1a2db2d796bc3847852a5c8dc2a1e6e83b:
Merge tag 'rust-ci-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2025-09-30 09:29:38 -0700)
are available in the Git repository at:
https://github.com/
From: Frank Chang
Since Tx FIFO is now implemented using "qemu/fifo8.h", remove the comment
that no longer reflects the current implementation.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-ID: <20250911160647.5710-4-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
-
From: Daniel Henrique Barboza
It has been awhile since the last sync. Let's bring QEMU hwprobe support
on par with Linux 6.17-rc4.
A lot of new RISCV_HWPROBE_KEY_* entities are added but this patch is
only adding support for ZICBOM_BLOCK_SIZE.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
From: Max Chou
According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This commit modifies the minimum VLEN based on the vector
extensions and introduces a check rule for VLEN and ELEN.
Extension Minimum VLEN
* V 128
* Zve6
From: TANG Tiancheng
Add support for defining a vmstate field which is a variable-length array
of pointers, and use this to define a VMSTATE_TIMER_PTR_VARRAY() which allows
a variable-length array of QEMUTimer* to be used by devices.
Message-id: 20250909-timers-v1-0-7ee18a9d8...@linux.alibaba.co
From: Sunil V L
RISC-V support is added only in ACPI 6.6. According to the ACPI 6.6
specification, the minor version of the Fixed ACPI Description Table
(FADT) should be 6, and the Multiple APIC Description Table (MADT)
should use revision 7. So, update the RISC-V FADT and MADT to reflect
correct
From: Vac Chen
pmp_is_in_range() prefers to match addresses within the interval
[start, end]. To archieve this, pmpaddrX is decremented during the end
address update.
In TOR mode, a rule is ignored if its start address is greater than or
equal to its end address.
However, if pmpaddrX is set to
From: Jay Chang
RISC-V Privileged Spec states:
"In harts with S-mode, the medeleg and mideleg registers must exist, and
setting a bit in medeleg or mideleg will delegate the corresponding trap
, when occurring in S-mode or U-mode, to the S-mode trap handler. In
harts without S-mode, the medeleg a
From: Jay Chang
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentiall
From: Xu Lu
When supervisor CSRs are accessed from VU-mode, a virtual instruction
exception should be raised instead of an illegal instruction.
Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
Signed-off-by: Xu Lu
Reviewed-by: Anup Patel
Reviewed-by: Nutty Liu
Message
From: Daniel Henrique Barboza
GETPC() should always be called from the top level helper, e.g. the
first helper that is called by the translation code. We stopped doing
that in commit 3157a553ec, and then we introduced problems when
unwinding the exceptions being thrown by helper_mret(), as report
From: Yang Jialong
The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.
Signed-off-by: Yang Jialong
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20250728055114.252024-1-z_baj...@yeah.
From: Sunil V L
Signed-off-by: Sunil V L
Acked-by: Michael S. Tsirkin
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Nutty Liu
Message-ID: <20250724110350.452828-2-suni...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file cha
From: Sunil V L
Update the expected tables for the version change.
/*
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 004h] Signature : "FACP"[Fixed ACPI
Description Table (FADT)]
[004
From: Daniel Henrique Barboza
We're missing a strace entry for riscv_hwprobe, and using -strace will
report it as "Unknown syscall 258".
After this patch we'll have:
$ ./build/qemu-riscv64 -strace test_mutex_riscv
110182 riscv_hwprobe(0x7f207efdc700,1,0,0,0,0) = 0
110182 brk(NULL) = 0x0
From: Daniel Henrique Barboza
This reverts commit 28c12c1f2f50d7f7f1ebfc587c4777ecd50aac5b.
As reported in [1] this commit is breaking Linux vector code, and
although a simpler reproducer was provided, the fix itself isn't trivial
due to the amount and the nature of the changes. And we really do
From: Alistair Francis
The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e:
Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250730-2
From: Jim Shu
Preparation commit to let aclint timer to use stimecmp write function.
Aclint timer doesn't call sstc() predicate so we need to check inside
the stimecmp write function.
Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Message-ID: <20250519143518.11086-2-jim@sifive.com>
Sign
From: Charalampos Mitrodimas
Add a regression test to verify that MEPC properly masks the lower
bits when an address with mode bits is written to it, as required by
the RISC-V Privileged Architecture specification.
The test sets STVEC to an address with bit 0 set (vectored mode),
triggers an ill
From: Alexandre Ghiti
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Reviewed-by: Deepak Gupta
Signed-off-by: Alexandre Ghiti
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Nutty Liu
Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8
From: Jim Shu
Support 4-byte atomic instruction fetch when instruction is natural
aligned.
Current implementation is not atomic because it loads instruction twice
for first and last 2 bytes. We load 4 bytes at once to keep the
atomicity. This instruction preload method only applys when instructi
From: Daniel Henrique Barboza
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza
Message-ID: <202505292
From: Charalampos Mitrodimas
According to the RISC-V Privileged Architecture specification, the low
bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits
must be zero.
This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and
the implicit reads by MRET/SRET instructi
From: Max Chou
According to the V spec, the vector fault-only-first load instructions
may change the VL CSR.
So the ldff_trans TCG translation function should generate the
lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
make sure the vl_eq_vlmax TB flag is correct.
Signed-
From: Florian Lugou
The current handler for TXFIFO writes schedules an async callback to
pop characters from the queue. When software writes to TXFIFO faster
than the async callback delay (100ns), the timer may be pushed back
while the previous character has not be dequeued yet. This happens in
p
From: Nutty Liu
The original implementation incorrectly performed a bitwise AND
operation between the PPN of iova and PPN Mask, leading to an
incorrect PPN field in Translation-reponse register.
The PPN of iova should be set entirely in the PPN field of
Translation-reponse register.
Also remove
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: "liu.xuem...@zte.com.cn"
Address an error in migration when aia is configured as 'aplic-imsic' in
riscv kvm vm by adding riscv_aplic_state_needed() and
riscv_imsic_state_needed() to determine whether the corresponding sates are
needed.
Previously, the fields in the vmsds of 'riscv_aplic' a
From: Anton Blanchard
fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Message-ID: <20250501114253.594887-1-ant...@tenstorrent.com>
Signed-off-by: Alista
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Huang Borong <3543977...@qq.com>
This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC devices. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Signed-off-by: qinshaoqing
Signe
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Vasilis Liaskovitis
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
and rd arguments are x0.
In this case, if the new property is true, only the vill bit will be set.
See
https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding
Acco
From: Daniel Henrique Barboza
These properties were deprecated in QEMU 8.2, commit 8043effd9b.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250530134608.1806922-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h
From: Joel Stanley
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Joel Stanley
Message-ID: <20250604025450.85327-4-j...@jms.id.au>
Signed-off-by: Alistair F
From: Huang Borong <3543977...@qq.com>
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized bas
From: Daniel Henrique Barboza
The SBI spec states, for console write byte:
"This is a blocking SBI call and it will only return after writing the
specified byte to the debug console. It will also return, with
SBI_ERR_FAILED, if there are I/O errors."
Being a blocker call will either succeed wri
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Daniel Henrique Barboza
'ssstrict' is a RVA23 profile-defined extension defined as follows:
"No non-conforming extensions are present. Attempts to execute
unimplemented opcodes or access unimplemented CSRs in the standard or
reserved encoding spaces raises an illegal instruction exception
From: Daniel Henrique Barboza
Björn reported in [1] a case where a rv64 CPU is going through the
profile code path to enable satp mode. In this case,the amount of
extensions on top of the rv64 CPU made it compliant with the RVA22S64
profile during the validation of CPU 0. When the subsequent CPUs
From: Joel Stanley
The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Signed-off-by: Joel Stanley
Message-ID: <20250604025450.85327-2-j...@jms.id.au>
Signed-off-by: Alistair Francis
From: Daniel Henrique Barboza
We have support for sdtrig for awhile but we are not advertising it. It
is enabled by default via the 'debug' flag. Use the same flag to also
advertise sdtrig.
Add an exception in disable_priv_spec_isa_exts() to avoid spamming
warnings for 'sdtrig' for vendor CPUs l
From: Jay Chang
Previously, the number of PMP regions was hardcoded to 16 in QEMU.
This patch replaces the fixed value with a new `pmp_regions` field,
allowing platforms to configure the number of PMP regions.
If no specific value is provided, the default number of PMP regions
remains 16 to pres
From: Daniel Henrique Barboza
We have code in riscv_cpu_add_profiles() to enable a profile right away
in case a CPU chose the profile during its cpu_init(). But we're using
the user callback option to do so, setting profile->user_set.
Create a new helper that does all the grunt work to enable/di
From: Jim Shu
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Message-ID: <20250519143518.11086-5-jim@sifive.com>
Signed-off-by: Alistair Francis
---
From: Joel Stanley
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-
From: Jim Shu
When changing the mtime value, the period of [s|vs]timecmp timers
should also be updated, similar to the period of mtimecmp timer.
The period of the stimecmp timer is the time until the next S-mode
timer IRQ. The value is calculated as "stimecmp - time". [1]
It is equal to "stimecm
From: Meng Zhuo
This patch adds max_satp_mode from host kvm cpu setting.
Tested on: Milkv Megrez (Eswin 7700x)
Reviewed-by: Andrew Jones
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
Signed-off-by: Meng Zhuo
Message-ID: <20250606034250.181707-1-mengz...@iscas.ac.cn>
Signed-off-
From: Alistair Francis
The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59:
Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into
staging (2025-07-03 06:01:41 -0400)
are available in the Git repository at:
https://github.com/alistair2
From: Daniel Henrique Barboza
Put it after zalrsc and before zawrs.
Cc: qemu-triv...@nongnu.org
Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250522113344.823294-1-dbarb...@ventanamicro.com>
Sig
From: Daniel Henrique Barboza
We're changing 'mmu' to true regardless of whether the profile is
being enabled or not, and at the same time we're changing satp_mode to
profile->enabled.
This will promote a situation where we'll set mmu=on without a virtual
memory mode, which is a mistake.
Only t
From: Jay Chang
According to the RISC-V Privileged Specification (version >1.12),
RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions
(pmpaddr0–pmpaddr63).
Signed-off-by: Jay Chang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Me
From: Jim Shu
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.
Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Message-ID: <20250519143518.11086-4-jim@sifive.com>
Signed-off-by: Alistair Francis
From: Alistair Francis
The following changes since commit 757a34115e7491744a63dfc3d291fd1de5297ee2:
Merge tag 'pull-nvme-20250515' of https://gitlab.com/birkelund/qemu into
staging (2025-05-15 13:42:27 -0400)
are available in the Git repository at:
https://github.com/alistair2
From: Max Chou
Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-9-max.c...@s
From: Max Chou
According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.
The vs1 EEW of vrgatherei16.vv is 16.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <
From: Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250429125811.224803-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --
From: Loïc Lefort
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3,
From: Daniel Henrique Barboza
Throughout the code we're accessing the board memmap, most of the time,
by accessing it statically via 'virt_memmap'. This static map is also
assigned in the machine state in s->memmap.
We're also passing it as a variable to some fdt functions, which is
unorthodox s
From: Max Chou
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-5-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
---
t
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250425152311.804338-2-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 3 +-
From: Paolo Savini
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface to probe_access and
probe
From: Daniel Henrique Barboza
Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and
create_fdt_rtc() to use s->memmap in their logic.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20250429125811.224803-9-dbarb...@ventanamicro.com>
Signed-off-by
From: Daniel Henrique Barboza
create_fdt_virtio() can use s->memmap instead of having an extra
argument for it.
While we're at it rewrite it a little bit to avoid the clunky line in
'name' and code repetition:
- declare 'virtio_base' out of the loop since it never changes;
- declare a 'size' va
From: Anton Blanchard
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Max Chou
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-2-ma
From: Daniel Henrique Barboza
'reglist' is being g-malloc'ed but never freed.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Message-ID: <20250429124421.223883-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Franc
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250425152311.804338-7-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/internals.h | 5
From: Daniel Henrique Barboza
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250422024752.2060289-1-alistair.fran...@wdc.com>
Signed-off-by: Alistair Francis
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 57dddc
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250425152311.804338-5-richard.hender...@linaro.org>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 8
From: Daniel Henrique Barboza
This change is motivated by a future change w.r.t CSRs management. We
want to handle them the same way as KVM extensions, i.e. a static array
with KVMCPUConfig objs that will be read/write during init and so on.
But to do that properly we must be able to declare a st
From: Max Chou
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Max Chou
Message-ID: <20250408103938.3623486-6-max.c...@sifive.com>
Signed-off-by: Alistair Francis
Cc: qemu-sta...@nongnu.org
---
t
From: Richard Henderson
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Reviewed-b
From: Sebastian Huber
Signed-off-by: Sebastian Huber
Acked-by: Alistair Francis
Message-ID: <20250319061342.26435-2-sebastian.hu...@embedded-brains.de>
Signed-off-by: Alistair Francis
---
hw/misc/mchp_pfsoc_sysreg.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/misc/mchp_pfsoc
From: Daniel Henrique Barboza
The function can receive the value via s->memmap[VIRT_FW_CFG].base from
the caller, avoiding the use of virt_memmap.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-ID: <20250429125811.224803-5-dbar
From: Daniel Henrique Barboza
Add support for the scounteren KVM CSR. Note that env->scounteren is a
32 bit and all KVM CSRs are target_ulong, so scounteren will be capped
to 32 bits read/writes.
Reported-by: Andrew Jones
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Review
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