sed s/Fixed the issue of/Fix/ <<<$SUBJECT
On Tue, Sep 09, 2025 at 05:09:17PM +0800, Xie Bo wrote:
> This patch fixes two migration issues for virtual machines in KVM mode:
Don't start commit messages with "This patch".
>
> 1.It saves and restores the vCPU's privilege mode to ensure that the v
Remove the dashes in the summary (Set-KVM-initial-privilege-mode).
On Tue, Sep 09, 2025 at 05:09:16PM +0800, Xie Bo wrote:
> For KVM mode, the privilege mode should not include M-mode, and the initial
> value should be set to S-mode. Additionally,patch 2 adds the implementation
> of putting th
Hi Coco,
On Fri, 2025-09-12 at 10:43 -0700, Coco Li wrote:
> Hello Andrew,
>
> I discussed with the original author of the patch and the Nuvoton
> functionality mentioned above has not been upstreamed since then,
> unfortunately.
Okay, so can you please update the commit message
reviewers
shouldn't need to look at them again.
Anyway, for the series (since I can't see any difference from before)
Reviewed-by: Andrew Jones
Thanks,
drew
> * The changes are purely mechanical; no code logic was altered *
> - Added 'Cc: qemu-sta...@nongnu.org'
>
; - Patch 2: unchanged; keep Reviewed-by from Andrew Jones
>
Except my r-b isn't on the patch...
>
> Xie Bo (2):
> Set KVM initial privilege mode and mp_state
> Fix VM resume after QEMU+KVM migration
>
> target/riscv/cpu.c | 17 +-
> target/ri
E_STOPPED;
> +}
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> if (env->misa_mxl > MXL_RV32) {
> /*
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 51e49e03de..4b1c5bf0e4 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -256,6 +256,8 @@ struct CPUArchState {
> #endif
>
> target_ulong priv;
> +/* Current multiprocessor state of this vCPU. */
> +uint32_t mp_state;
> /* CSRs for execution environment configuration */
> uint64_t menvcfg;
> target_ulong senvcfg;
> --
> 2.43.0
>
Reviewed-by: Andrew Jones
_version_id = 10,
> +.version_id = 11,
> +.minimum_version_id = 11,
> .post_load = riscv_cpu_post_load,
> .fields = (const VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -422,6 +422,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UNUSED(4),
> VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> +VMSTATE_UINT32(env.mp_state, RISCVCPU),
> VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
> VMSTATE_UINT64(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> --
> 2.43.0
>
Reviewed-by: Andrew Jones
On Wed, Sep 10, 2025 at 05:35:27PM +0800, Xie Bo wrote:
> For KVM mode, the privilege mode should not include M-mode, and the
> initial value should be set to S-mode. Additionally, a following patch
> adds the implementation of putting the vCPU privilege mode to KVM.
> When the vCPU runs for the
d a quick look and
couldn't immediately see an equivalent implementation.
Regardless, I'd like to see more motivation in the commit message than
"make it behave like Nuvoton". Can you provide a concrete use-case as
an example?
Andrew
Signed-off-by: Andrew Keesler
On Tue, Sep 9, 2025 at 5:19 AM Daniel P. Berrangé
wrote:
> On Tue, Sep 02, 2025 at 02:13:12PM +0000, Andrew Keesler wrote:
> > In 454f4b0f, we started down the path of supporting separate
> > configurations per display head (e.g., you have 2 h
scv: add RISC-V IOMMU base emulation")
Signed-off-by: Andrew Jones
---
hw/riscv/riscv-iommu.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 96a7fbdefcf3..155190d032dd 100644
--- a/hw/riscv/riscv-io
after v2 review
* fix new resolution configuration logic (&& instead of ||)
* correct use of api machinery (has_*)
* move documentation to QMP API
* v2: changes after v1 review + 10.2 rebase
* updated code, commit message, and cover letter to match new res config logic
* marked n
In 454f4b0f, we started down the path of supporting separate
configurations per display head (e.g., you have 2 heads - one with
EDID name "AAA" and the other with EDID name "BBB").
In this change, we add resolution to this configuration surface (e.g.,
you have 2 heads - one with resolution 111x222
Trying some other x86 maintainers this time...
~Andrew
On 25/07/2025 1:01 pm, Andrew Cooper wrote:
> Ping again?
>
> ~Andrew
>
> On 20/05/2025 5:32 pm, Andrew Cooper wrote:
>> Ping?
>>
>> On 12/03/2025 12:06 am, Andrew Cooper wrote:
>>> While the
In 454f4b0f, we started down the path of supporting separate
configurations per display head (e.g., you have 2 heads - one with
EDID name "AAA" and the other with EDID name "BBB").
In this change, we add resolution to this configuration surface (e.g.,
you have 2 heads - one with resolution 111x222
es)
Behavior: new behavior - outputs[i] enabled with outputs[i].xres/yres
Case: (xres || yres) && (outputs[i].xres || outputs[i].yres)
Behavior: new behavior - outputs[i] enabled with outputs[i].xres/yres
Changelist:
* v2: changes after v1 review + 10.2 rebase
* updated code, commit messag
not sure how to detect if xres/yres has been set globally
to 1280x800, or if we are just getting the defaults.
What do you think?
On Wed, Aug 27, 2025 at 12:44 PM Daniel P. Berrangé
wrote:
> On Wed, Aug 27, 2025 at 11:48:34AM -0400, Andrew Keesler wrote:
> > Sending again (replying
will require an explicit "Since 10.2" tag against them, separate
> from the overall struct versrion below.
ACK - fixed for the next patch.
> This is a backcompat problem, because xres/yres are mandatory if
> 'outputs' is present.
ACK - fixed for the next patch.
On We
On Fri, Aug 01, 2025 at 05:52:20PM +0800, 谢波 wrote:
> This is v4 of this patch to add the function of saving and restoring the
> running status of vCPU during migration
>
> This patch fixes two critical bugs in QEMU with KVM:
> Post-Migration Failure in User Mode: When QEMU with KVM is running in
Ping again?
~Andrew
On 20/05/2025 5:32 pm, Andrew Cooper wrote:
> Ping?
>
> On 12/03/2025 12:06 am, Andrew Cooper wrote:
>> While the (intno << shift) expression is correct for indexing the IDT based
>> on
>> whether Long Mode is active, the error code itself wa
_conf.outputs are provided, then
virtio_gpu_base_conf.outputs.xres/virtio_gpu_base_conf.outputs.yres
will take precedence. In this case,
virtio_gpu_base_conf.outputs.xres/virtio_gpu_base_conf.outputs.yres
must be non-zero.
Signed-off-by: Andrew Keesler
---
hw/display/virtio-gpu-base.c | 12
_conf.outputs are provided, then
virtio_gpu_base_conf.outputs.xres/virtio_gpu_base_conf.outputs.yres
will take precedence. In this case,
virtio_gpu_base_conf.outputs.xres/virtio_gpu_base_conf.outputs.yres
must be non-zero.
Andrew Keesler (1):
hw/display: Support per-head resolutions with virtio-gpu
hw/display/virtio-gpu-base.c | 12
qapi/virtio.json | 6 +-
2 files changed, 17 insertions(+), 1 deletion(-)
--
2.50.0.727.gbf7dc18ff4-goog
On Wed, Jul 16, 2025 at 03:47:37PM +0800, BillXiang wrote:
> Consider a system with 8 harts, where each hart supports 5
> Guest Interrupt Files (GIFs), yielding 40 total GIFs.
> If we launch a QEMU guest with over 5 vCPUs using
> "-M virt,aia='aplic-imsic' -accel kvm,riscv-aia=hwaccel" – which
> re
"name":"AAA"
},
{
"name":"BBB"
}
]}'
Signed-off-by: Andrew Keesler
---
hw/core/qdev-properties-system.c| 44 +
hw/display/virtio-gpu-base.c| 27 ++
-paste issue in virtio_gpu_base_generate_edid()
* v3 - report an error at realize time if request name is too long
* v2 - migrated configuration surface to virtio-gpu device
Andrew Keesler (1):
hw/display: Allow injection of virtio-gpu EDID name
hw/core/qdev-properties-system.c| 44 ++
"name":"AAA",
},
{
"name":"BBB",
}
]}'
Signed-off-by: Andrew Keesler
---
hw/core/qdev-properties-system.c| 44 +
hw/display/virtio-gpu-base.c| 27 ++
id()
* v3 - report an error at realize time if request name is too long
* v2 - migrated configuration surface to virtio-gpu device
Andrew Keesler (1):
hw/display: Allow injection of virtio-gpu EDID name
hw/core/qdev-properties-system.c| 44 +
hw/display/virti
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Changelog:
* v4 - fixed copy-paste issue in virtio_gpu_base_generate_edid()
* v3 - report an error at realize time if request name is too long
* v2 - m
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Signed-off-by: Andrew Keesler
---
hw/core/qdev-properties-system.c| 44 +
hw/display/virtio-gpu-base.c| 26 +
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Signed-off-by: Andrew Keesler
---
hw/core/qdev-properties-system.c| 44 +
hw/display/virtio-gpu-base.c| 26 +
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Andrew Keesler (1):
hw/display: Allow injection of virtio-gpu EDID name
hw/core/qdev-properties-system.c| 44 +
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Andrew Keesler (1):
hw/display: Allow injection of virtio-gpu EDID name
hw/core/qdev-properties-system.c| 44 +
"name":"AAA",
},
{
"name":"BBB",
},
]}'
Signed-off-by: Andrew Keesler
---
hw/core/qdev-properties-system.c| 44 +
hw/display/virtio-gpu-base.c| 20 +++
On Mon, Jun 23, 2025 at 06:39:02PM -0300, Daniel Henrique Barboza wrote:
> Hi Radim,
>
> It seems like this patch is breaking 'make check-functional':
>
> 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT
> 90.06s killed by signal 15 SIGTERM
>
> Checking the lo
it for all. See the list below for the
> brave.
My involvement has dropped off quite a bit, but for what it's worth,
this seems sensible to me :)
Andrew
The word 'find' appears twice, remove the extra one.
Signed-off-by: Andrew Kreimer
---
docs/system/introduction.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst
index 338d3745c3..4cd46b5b8f 100644
ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> --
> 2.49.0
>
>
Reviewed-by: Andrew Jones
-by: Daniel Henrique Barboza
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/server_platform_ref.c | 78 --
> 2 files changed, 75 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones
On Wed, May 28, 2025 at 05:01:28PM -0300, Daniel Henrique Barboza wrote:
> From: Fei Wu
>
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RI
(def->profile) {
> assert(profile_extends(def->profile, mcc->def->profile));
> -assert(mcc->def->bare);
> mcc->def->profile = def->profile;
> }
> if (def->misa_mxl_max) {
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
On Wed, May 28, 2025 at 05:01:27PM -0300, Daniel Henrique Barboza wrote:
> From: Fei Wu
>
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> a virt CPU type (rvsp-ref) as compliant as possible.
>
>
/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
I gave my r-b on the last version of this patch (please include those when
posting again without major changes), here it is again
Reviewed-by: Andrew Jones
drew
> ---
> target/riscv/cpu.c | 3 +--
> target/riscv/cpu.h
ote a situation where we'll set mmu=on without a virtual
> memory mode, which is a mistake.
>
> Only touch 'mmu' and satp_mode if the profile is being enabled.
>
> Suggested-by: Andrew Jones
> Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
&
-1396,7 +1403,7 @@ static void cpu_get_profile(Object *obj, Visitor *v,
> const char *name,
> static void riscv_cpu_add_profiles(Object *cpu_obj)
> {
> for (int i = 0; riscv_profiles[i] != NULL; i++) {
> -const RISCVCPUProfile *profile = riscv_profiles[i];
> +RISCVCPUProfile *profile = riscv_profiles[i];
>
> object_property_add(cpu_obj, profile->name, "bool",
> cpu_get_profile, cpu_set_profile,
> @@ -1408,7 +1415,7 @@ static void riscv_cpu_add_profiles(Object *cpu_obj)
> * case.
> */
> if (profile->enabled) {
> -object_property_set_bool(cpu_obj, profile->name, true, NULL);
> +riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true);
> }
> }
> }
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
t;name;
> -parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name,
> NULL);
> -profile->enabled = parent_enabled;
> +profile->present = parent->present;
> }
>
> static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> @@ -910,7 +905,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> }
> }
>
> -profile->enabled = profile_impl;
> +profile->present = profile_impl;
>
> riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
> riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
Ping?
On 12/03/2025 12:06 am, Andrew Cooper wrote:
> While the (intno << shift) expression is correct for indexing the IDT based on
> whether Long Mode is active, the error code itself was unchanged with AMD64,
> and is still the index with 3 bits of metadata in the bottom.
>
&g
On Tue, May 20, 2025 at 01:58:45PM +0200, Andrew Jones wrote:
> On Tue, May 20, 2025 at 06:41:03PM +0800, Meng Zhuo wrote:
> > This patch adds host satp mode while kvm/host cpu satp mode is not
> > set.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2
bject *cpu_obj)
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> kvm_riscv_init_cfg(cpu, &kvmcpu);
> +kvm_riscv_init_satp_mode(cpu, &kvmcpu);
>
> kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
> }
> @@ -1980,7 +1998,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **errp)
> }
> }
>
> - return true;
> +return true;
> }
>
> void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> --
> 2.39.5
>
>
Otherwise,
Reviewed-by: Andrew Jones
On Tue, May 20, 2025 at 07:50:15AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/20/25 4:50 AM, Andrew Jones wrote:
> > On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 5/19/25 1:35 PM, Andrew Jones wr
On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/19/25 1:35 PM, Andrew Jones wrote:
> > On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 5/16/25 9:23 AM, Alexandre Ghiti
On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/16/25 9:23 AM, Alexandre Ghiti wrote:
> > The satp mode is set using the svXX properties, but that actually
> > restricts the satp mode to the minimum required by the profile and
> > prevents the use of higher sat
bit CSR in a
> 32 bit field when running in a 64 bit CPU.
>
> To prevent that, change the current logic to honor the size of the QEMU
> storage instead of the KVM CSR reg.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/ris
bit CSR in a
> 32 bit field when running in a 64 bit CPU.
>
> To prevent that, change the current logic to honor the size of the QEMU
> storage instead of the KVM CSR reg.
>
> Signed-off-by: Daniel Henrique Barboza
> Suggested-by: Andrew Jones
> ---
> target/riscv
On Mon, Apr 28, 2025 at 04:23:14PM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> In this new version a change was made in patch 8. Instead of changing
> scounteren to target_ulong, change the current logic to honor the QEMU
> env storage instead of the KVM reg size.
>
> This will make QEMU the
On Mon, Apr 28, 2025 at 03:37:26PM +0200, Radim Krčmář wrote:
> 2025-04-28T14:08:59+02:00, Andrew Jones :
> > On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote:
> >> 2025-04-28T09:00:55+02:00, Andrew Jones :
> >> > On Sun, Apr 27, 2025 at 09:25:57PM +0800,
On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote:
> 2025-04-28T09:00:55+02:00, Andrew Jones :
> > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
> >> This patch adds host satp mode while kvm/host cpu satp mode is not
> >> set.
> >
> &g
On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
Huh, the KVM side[1] was written for this purpose, but it appears we never
got a QEMU side merged.
[1] commit 2776421e6839 ("RISC-V: KVM: provide UAPI for host SA
On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote:
> We want to support scounteren as a KVM CSR. The KVM UAPI defines every
> CSR size as target_ulong, and our env->scounteren is fixed at 32 bits.
>
> The other existing cases where the property size does not match the KVM
> r
KVM to read/write the
> scounteren CSR without any surprises.
>
> Aside from bumping the version of the RISCVCPU vmstate no other
> behavioral changes are expected.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.h | 9 ++++-
> target/riscv/machine.c | 6 +++---
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones
On Fri, Apr 25, 2025 at 08:37:05AM -0300, Daniel Henrique Barboza wrote:
> Now that CPURISCVState::scounteren is a target_ulong, add support for
> the scounteren KVM CSR.
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-c
On Fri, Apr 25, 2025 at 08:37:04AM -0300, Daniel Henrique Barboza wrote:
> We want to support scounteren as a KVM CSR. The KVM UAPI defines every
> CSR size as target_ulong, and our env->scounteren is fixed at 32 bits.
>
> The other existing cases where the property size does not match the KVM
> r
On Fri, Apr 25, 2025 at 08:37:03AM -0300, Daniel Henrique Barboza wrote:
> We're missing the senvcfg CSRs which is already present in the
> KVM UAPI.
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
>
since we
> @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu,
> KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, reglist);
> +kvm_riscv_read_csr_cfg(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
> @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj)
>
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> -kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
> +kvm_riscv_init_cfg(cpu, &kvmcpu);
>
> kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
> }
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
r_cfg);
> +} else {
> +g_assert_not_reached();
> +}
>
> -KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
> -KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
> -KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
> -KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
> -KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
> -KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
> -KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
> -KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
> -KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
> +ret = kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®);
> +if (ret) {
> +return ret;
> +}
> +}
>
> return 0;
> }
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
s)
> return ret;
> }
>
> -id = RISCV_CONFIG_REG(env, marchid);
> +id = RISCV_CONFIG_REG(marchid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid);
> if (ret != 0) {
> return ret;
> }
>
> -id = RISCV_CONFIG_REG(env, mimpid);
> +id = RISCV_CONFIG_REG(mimpid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid);
>
> return ret;
> @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> if (cpu->cfg.ext_zicbom &&
> riscv_cpu_option_set(kvm_cbom_blocksize.name)) {
>
> -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
> +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,
> kvm_cbom_blocksize.kvm_reg_id);
> reg.addr = (uint64_t)&val;
> ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®);
> @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> if (cpu->cfg.ext_zicboz &&
> riscv_cpu_option_set(kvm_cboz_blocksize.name)) {
>
> -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
> +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,
> kvm_cboz_blocksize.kvm_reg_id);
> reg.addr = (uint64_t)&val;
> ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®);
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx)
>
> -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx)
> +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx)
>
> #define RISCV_VECTOR_CSR_REG(env, name) \
> kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
| 29 ++---
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
Reviewed-by: Andrew Jones
On Fri, Apr 25, 2025 at 08:36:58AM -0300, Daniel Henrique Barboza wrote:
> 'reglist' is being g+malloc'ed but never freed.
g_malloc'ed
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm
+1920,7 @@ static void virt_machine_class_init(ObjectClass *oc,
> void *data)
> mc->desc = "RISC-V VirtIO board";
> mc->init = virt_machine_init;
> mc->max_cpus = VIRT_CPUS_MAX;
> -mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +mc->default_cpu_type = TYPE_RISCV_CPU_MAX;
> mc->block_default_type = IF_VIRTIO;
> mc->no_cdrom = 1;
> mc->pci_allow_0_address = true;
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
On Wed, Apr 23, 2025 at 04:45:29PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 4/23/25 12:15 PM, Andrew Jones wrote:
...
> > if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) {
> > kvm_cpu_csr_set_u32(cpu, csr_cfg, reg);
> > } else if (KV
On Thu, Apr 17, 2025 at 09:48:39AM -0300, Daniel Henrique Barboza wrote:
> The Linux kernel, up until at least version 6.12, has issues with a KVM
> guest setting scounteren to 0 during reset. No error will be thrown
> during boot, but trying to use rdtime in the guest (by executing 'ping'
> for ex
On Thu, Apr 17, 2025 at 09:48:38AM -0300, Daniel Henrique Barboza wrote:
> We're missing scounteren and senvcfg CSRs, both already present in the
> KVM UAPI.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
The patch changed enough that it's n
On Thu, Apr 17, 2025 at 09:48:37AM -0300, Daniel Henrique Barboza wrote:
> [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6.
> This happens because the kernel does not know 'senvcfg', making it
> unable to boot because QEMU is reading/wriiting it without any checks.
>
> Afte
On Thu, Apr 17, 2025 at 09:48:36AM -0300, Daniel Henrique Barboza wrote:
> At this moment we're not checking if the host has support for any
> specific CSR before doing get/put regs. This will cause problems if the
> host KVM doesn't support it (see [1] as an example).
>
> We'll use the same appro
entations are 32-bit.
> Set min/max access_size accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jeffery
On Fri, Apr 04, 2025 at 02:37:32PM +0200, Philippe Mathieu-Daudé wrote:
> On 4/4/25 13:30, Daniel Henrique Barboza wrote:
> >
> >
> > On 4/4/25 2:50 AM, Alistair Francis wrote:
> > > On Fri, Mar 28, 2025 at 2:16 AM Philippe Mathieu-Daudé
> > > wrote:
> > > >
> > > > On 27/3/25 14:02, Daniel Hen
ast2500 and
> ast2600 datasheets.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636
> Signed-off-by: Joel Stanley
> Reviewed-by: Troy Lee
> Message-ID: <20241118021820.4928-1-j...@jms.id.au>
> [PMD: Rebased, only including SCU changes]
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jeffery
eady present in the
> > > KVM UAPI.
> > >
> > > Signed-off-by: Daniel Henrique Barboza
> > > Reviewed-by: Andrew Jones
> >
> > Acked-by: Alistair Francis
>
> This patch seems to have broken KVM acceleration for me:
>
> $ ./build/qemu-sy
ted to
being told there was an error with IDT index 256 when INT $0x80 (128) was the
problem instruction:
...
Error: Unexpected fault 0x800d0802, #GP[IDT[256]]
...
Fixes: d2fd1af76777 ("x86_64 linux user emulation")
Signed-off-by: Andrew Cooper
---
CC: Paolo Bonzini
CC: Richa
On Mon, Feb 24, 2025 at 04:24:13PM +0800, Yong-Xuan Wang wrote:
> Support user-space emulation of SIREG and STOPEI CSR with KVM
> acceleration. For SIREG emulation, the SISELECT CSR value and iprio
> array must be loaded before handling, and since the iprio array might
> be modified, it must be wri
On Mon, Feb 24, 2025 at 04:24:12PM +0800, Yong-Xuan Wang wrote:
> Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation
> in user space with KVM acceleration. This update reuses the TCG CSR
> emulation function to simplify the implementation and reduce the
> redundant work. Also it
se {
> +rcpu->cfg.ext_smaia = true;
> +}
> }
> +
> riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
>riscv_imsic_rmw, imsic);
> }
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
controller
> from
> - the irqchip. See :ref:`riscv-aia` for more details on all available AIA
> - modes.
> + the in-kernel irqchip. Or the kernel irqchip can be disabled by using
> + "-accel kvm,kernel-irqchip=off". In this case the ``virt`` machine will
> + emulate the APLIC and IMSIC controller in user-space instead of using
> in-kernel
> + irqchip. See :ref:`riscv-aia` for more details on all available AIA modes.
>
> - aia-guests=nnn
>
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, Feb 24, 2025 at 04:24:09PM +0800, Yong-Xuan Wang wrote:
> Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA
> extension in VS mode.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/kvm/kvm-cpu.c | 45 ++
> 1 file changed, 45 inserti
R_TABLE_SIZE);
>
> +return csr_ops[csr_no].name;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> target_ulong riscv_new_csr_seed(target_ulong new_value,
> target_ulong write_mask);
>
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, Feb 24, 2025 at 04:24:10PM +0800, Yong-Xuan Wang wrote:
> Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of
> Smstateen extension in VS mode.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/kvm/kvm-cpu.c | 25 +
> 1 file changed, 25 insertio
REG(scause), env->scause);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp);
>
Hi Patrick,
On Thu, 2025-02-27 at 15:42 +, Patrick Venture wrote:
> eth_hdr requires 2 byte alignment
>
> Signed-off-by: Patrick Venture
> ---
> hw/net/ftgmac100.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac10
a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index ea8d77d06a..c93612b1da 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -360,6 +360,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
>
> cpu->cfg.ext_sha = r
FG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
> KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT),
> KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
> +KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC),
> };
>
> static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg)
> --
> 2.48.1
>
>
Reviewed-by: Andrew Jones
SCV_SET_CSR(cs, env, scounteren, env->scounteren);
> +KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg);
>
> return 0;
> }
> --
> 2.48.1
>
Reviewed-by: Andrew Jones
pu->env.fdt_addr; /* a1 */
> -env->satp = 0;
> -env->mie = 0;
> -env->stvec = 0;
> -env->sscratch = 0;
> -env->sepc = 0;
> -env->scause = 0;
> -env->stval = 0;
> -env->mip = 0;
> +
> +kvm_riscv_reset_regs_csr(env);
> }
>
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> --
> 2.48.1
>
Reviewed-by: Andrew Jones
On Tue, Feb 18, 2025 at 01:38:53PM -0300, Daniel Henrique Barboza wrote:
> At this moment ziccrse is a TCG always enable ext that has no flag. KVM
> will expose ziccrse to users, allowing them to turn it on/off.
KVM won't allow this to be disabled, since it can't be (there's no way
to turn off the
On Fri, Feb 21, 2025 at 09:45:35AM +0100, Andrew Jones wrote:
> On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> > Explictly reset env->mstatus and env->sie.
>
> mie was already getting set to zero, so that should have just been renamed
> in the
On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> Explictly reset env->mstatus and env->sie.
mie was already getting set to zero, so that should have just been renamed
in the last patch, but I still think we should drop the last patch.
> Add a comment about env->mip
> bei
On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote:
> Using env->sie is clearer than using env->mie.
Maybe? Just as sstatus is a subset of mstatus, sip and sie can be
subsets of mip and mie. However, the AIA can change sip/sie so they
no longer alias mip/mie, which is why we h
m/kvm-cpu.c
> index 23ce779359..484b6afe7c 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1603,9 +1603,6 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> CPURISCVState *env = &cpu->env;
> int i;
>
> -if (!kvm_enabled()) {
> -return;
> -}
> for (i = 0; i < 32; i++) {
> env->gpr[i] = 0;
> }
> --
> 2.48.1
>
>
Reviewed-by: Andrew Jones
On Tue, 2025-02-18 at 08:35 +0100, Cédric Le Goater wrote:
> The SoC type name is stored under AspeedSoCClass which is
> redundant. Use object_get_typename() instead where needed.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
at least, was) tied to qemu-system-i386 was using
Qemu as a XenBlk <-> QCOW adapter, at which point it wasn't even really
a system emulator, just a paravirtual disk implementation.
This is, AIUI, what ARM wants with the xenpv machine. If there's a
better way to do this, please do say.
Looking through Xen's CI, I can't see any of the ARM builds building
QEMU at all. I think it's quite possible it's not tested any more.
~Andrew
On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote:
> Add a helper function to get CSR name from CSR number.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/cpu.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/c
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