On Thu, Oct 03, 2024 at 10:06:11AM GMT, Daniel Henrique Barboza wrote:
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> > > +/*
> > > + * RISCV IOMMU Addre
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
> +/*
> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> + *
> + * Note: Code is based on get_physical_address() from
> target/riscv/cpu_helper.c
> + * Both implementation can be merged into single helper func
On Tue, Oct 01, 2024 at 09:05:52PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 10/1/24 8:28 PM, Tomasz Jeznach wrote:
> > On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
> > wrote:
> > >
> > >
> > >
> > > On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
> > > > On Fri, Aug 23, 2024 at 5:42
> It should only clear bit 0 in index mode and the correct result
> should be as following.
>
>set->int_status == 0b11
>s->pending == 2
>
>pending == 1
>s->pending == 1
>set->int_status == 0b10
>
Maybe this is a bit forward, but:
Sug
patible AST2700.
> Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback functions
> and aspeed_gpio_2700_ops memory region operation for AST2700.
> Introduce a new ast2700 class to support AST2700.
>
> Signed-off-by: Jamin Lin
Some of the wrapping in the commit message could be improved, but
otherwise:
Reviewed-by: Andrew Jeffery
; +assert(s->pending >= pending);
> +s->pending -= pending;
> +}
> +set->int_status = deposit32(set->int_status, pin_idx, 1, 0);
> +}
> +}
I think you can apply the same reasoning here as on the previous patch.
Andrew
*/
assert(s->pending >= pending);
/* No change to s->pending if pending is 0 */
s->pending -= pending;
/*
* The write acknowledged the interrupt regardless of whether it
* was pending or not. The post-condition is that it mustn't be
* pending. Unconditionally clear the status bit.
*/
s->int_status = deposit32(set->int_status, pin_idx, 1, 0);
}
Thoughts?
Up to you whether you keep the comments if the idea makes sense and you
choose to adopt it.
Andrew
commit 6df664f87c73 ("Revert "hw/riscv/virt.c: imsics DT: add
'#msi-cells'"") removed #msi-cells. Now that we have a Linux
commit to reference add a comment explaining why it was removed
to avoid it getting added back due to DT validation failures.
Signed-off-b
FS, env->misa_mxl);
> +for (int regnr = 0; regnr < 32; ++regnr) {
> +env->fpr[regnr] = 0;
> +}
> +riscv_csrrw(env, CSR_FCSR, NULL, 0, -1);
> +}
> #ifndef CONFIG_USER_ONLY
> env->misa_mxl = mcc->misa_mxl_max;
> env->priv = PRV_M;
> --
> 2.45.2
>
Reviewed-by: Andrew Jones
On Tue, 2024-09-24 at 06:48 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Andrew,
> >
> > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > >
On Tue, 2024-09-24 at 03:03 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Jamin,
> >
> > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> >
> > > +
> > &
cb, KVM_RISCV_ISA_EXT_ZCB),
> +KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD),
> +KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF),
> KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
> KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
> KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
t; + "%s: offset 0x%" PRIx64 " out of bounds\n",
> + __func__, offset);
> + return;
> +}
> +
> +switch (reg) {
> +case R_GPIO_2700_DEBOUNCE_TIME_1 ... R_GPIO_2700_DEBOUNCE_TIME_3:
> +idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1;
> +
> +if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) {
> +qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: debounce index: %d out of bounds\n",
> + __func__, idx);
> +return;
> +}
> +
> +s->debounce_regs[idx] = (uint32_t) data;
> +break;
> +case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL:
> +pin = reg - R_GPIO_A0_CONTROL;
> +
> +if (pin >= agc->nr_gpio_pins) {
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin number: %d\n",
> + __func__, pin);
> +return;
> +}
> +
> +if (SHARED_FIELD_EX32(data, GPIO_CONTROL_RESERVED)) {
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid reserved data: 0x%"
> + PRIx64"\n", __func__, data);
> +return;
> +}
> +
> +aspeed_gpio_write_control_reg(s, pin, type, data);
> +break;
> +default:
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
> + PRIx64"\n", __func__, offset);
> +break;
> +}
> +
> +return;
> +}
> +
> /** Setup functions **/
Bit of a nitpick, but I'm not personally a fan of banner comments like
this.
Andrew
On Wed, Sep 18, 2024 at 03:49:39PM GMT, Heinrich Schuchardt wrote:
> On 18.09.24 15:12, Peter Maydell wrote:
> > On Wed, 18 Sept 2024 at 14:06, Heinrich Schuchardt
> > wrote:
> > > Thanks Peter for looking into this.
> > >
> > > QEMU's cpu_synchronize_all_post_init() and
> > > do_kvm_cpu_synchron
On Wed, Sep 18, 2024 at 04:37:12PM GMT, Aleksei Filippov wrote:
>
>
> On 17.09.2024 16:10, Andrew Jones wrote:
> > On Tue, Sep 17, 2024 at 02:29:41PM GMT, Andrew Jones wrote:
> > > On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> > > > k
On Tue, Sep 17, 2024 at 06:45:21PM GMT, Heinrich Schuchardt wrote:
...
> When thinking about the migration of virtual machines shouldn't QEMU be in
> control of the initial state of vcpus instead of KVM?
>
Thinking about this more, I'm inclined to agree. Initial state and reset
state should be tra
On Tue, Sep 17, 2024 at 03:28:42PM GMT, Heinrich Schuchardt wrote:
> On 17.09.24 14:13, Andrew Jones wrote:
> > On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote:
> > > OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
> &
On Tue, Sep 17, 2024 at 02:29:41PM GMT, Andrew Jones wrote:
> On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new error p
On Mon, Sep 09, 2024 at 01:27:05PM GMT, Alistair Francis wrote:
> On Tue, Aug 6, 2024 at 7:05 AM Gregor Haas wrote:
> >
> > This patch series adds support for specifying OpenSBI domains on the QEMU
> > command line. A simple example of what this looks like is below, including
> > mapping the board
On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not
> trigger qemu abort with vendor-specific sbi.
>
> Add new error path to provide proper error in case of
> qemu_chr_fe_read_all() may not return sizeof(ch), because e
On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote:
> OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
> should do the same.
>
> Without this patch EDK II with TLS enabled crashes when hitting the first
> floating point instruction while running QEMU with --ac
On Mon, Sep 09, 2024 at 12:41:24PM GMT, Alistair Francis wrote:
> On Mon, Aug 19, 2024 at 5:50 PM Andrew Jones wrote:
> >
> > On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> > > On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones
> > > wrote:
>
resses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
use hwaddr for the mask, which, even on rv32, is 64-bits wide.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP
entries.")
Signed-off-
On Fri, Aug 30, 2024 at 02:05:05PM GMT, Vladimir Isaev wrote:
> Hi Andrew,
>
> 29.08.2024 11:40, Andrew Jones wrote:
> > While the spec doesn't state it, setting timecmp to UINT64_MAX is
> > another way to stop a timer, as it's considered setting the next
>
deliver
an interrupt at that previous timecmp time. Ensure the stopped timer
will not still deliver an interrupt by also deleting the QEMU timer
in the UINT64_MAX special case.
Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp
== UINT64_MAX")
Signed-off-by: Andre
bit setting.
Signed-off-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f6e3156b8d2f..341af901c5b0 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm
On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones wrote:
> >
> > Older firmwares and OS kernels which use deprecated device tree
> > properties or are missing support for new properties may not be
> > toleran
On Thu, Aug 01, 2024 at 12:43:24PM GMT, Daniel Henrique Barboza wrote:
> From: Tomasz Jeznach
>
> The RISC-V IOMMU specification is now ratified as-per the RISC-V
> international process. The latest frozen specifcation can be found at:
>
> https://github.com/riscv-non-isa/riscv-iommu/releases/do
9.1 since
it's a fix. The second patch allows users to bring it back by enabling
a new machine property 'strict-dt' which is meant to be used for cases
like these going forward. There's no rush for the second patch.
[1] https://lore.kernel.org/all/20240816124957.130017-2-ajo..
16124957.130017-2-ajo...@ventanamicro.com/ # 1
Signed-off-by: Andrew Jones
---
hw/riscv/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9981e0f6c9b9..cef41c150aaf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -552,7 +552,6 @@ static void create_fdt_one_im
t DT and know their software supports it, introduce a machine
property 'strict-dt' to do so. We also drop the one redundant
property that uses a deprecated name when strict-dt is enabled.
Signed-off-by: Andrew Jones
---
docs/system/riscv/virt.rst | 11 ++
hw/riscv/virt.c
t;
> hw/char/serial-isa.c:#include "hw/char/serial.h"
> hw/char/serial-pci.c:#include "hw/char/serial.h"
>
> Signed-off-by: Bernhard Beschow
> ---
> include/hw/arm/aspeed_soc.h | 2 +-
...
> hw/arm/aspeed_ast2400.c | 2 +-
> hw/arm/aspeed_soc_common.c | 2 +-
For the Aspeed bits:
Tested-by: Andrew Jeffery
-mc->max_cpus = 1;
>>> +/* MAX number of vcpus supported by Xen. */
>>> + mc->max_cpus = GUEST_MAX_VCPUS;
The only suitable number here is the one you get back from XEN_DMOP_nr_vcpus
GUEST_MAX_VCPUS is and has always been bogus as a compile time constant
in the Xen public headers (yes, ARM inherited it from x86, but it should
have never been copied to start with). Please do not introduce any
further uses of it.
~Andrew
On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote:
> On 13/8/24 10:00, Andrew Jones wrote:
> > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> > > On 8/13/24 17:13, Andrew Jones wrote:
> > > > C doesn't extend the sign bit f
On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> On 8/13/24 17:13, Andrew Jones wrote:
> > C doesn't extend the sign bit for unsigned types since there isn't a
> > sign bit to extend. This means a promotion of a u32 to a u64 results
> > in the uppe
resses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
revert to using target_long, since a signed type will get extended.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP
entries.")
Si
On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote:
> Counter delegation/configuration extension requires the following
> extensions to be enabled.
>
> 1. Smcdeleg - To enable counter delegation from M to S
> 2. S[m|s]csrind - To enable indirect access CSRs
> 3. Smstateen - Indirect CSR ext
On Tue, Aug 06, 2024 at 11:51:20AM GMT, Alistair Francis wrote:
> On Wed, Jul 24, 2024 at 9:33 AM Atish Patra wrote:
> >
> > Sscofpmf has been supported on virt machine for a long time. It is
> > required to enable profiling on virt machines. Let's enable it
> > by default for ease of usage.
> >
>
On Wed, Jul 31, 2024 at 01:27:09PM GMT, Daniel Henrique Barboza wrote:
> Hi Jason,
>
>
> On 7/23/24 12:25 PM, Jason Chien wrote:
> > Hi Daniel,
> >
> > On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote:
> > > From: Andrew Jones
>
On Wed, Jul 31, 2024 at 08:30:46AM GMT, Markus Armbruster wrote:
> I apologize for the delay.
>
> Daniel Henrique Barboza writes:
>
> > We're not honouring KVM options that are provided by any -accel option
> > aside from the first. In this example:
> >
> > qemu-system-riscv64 -accel kvm,riscv-a
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is t
On Thu, Jul 18, 2024 at 06:07:37PM GMT, Alexandre Ghiti wrote:
> The Svvptc extension describes a uarch that does not cache invalid TLB
> entries: that's the case for qemu so there is nothing particular to
> implement other than the introduction of this extension.
>
> Since qemu already exposes Sv
its/aspeed-9.1
I built the series using the tree you linked above. It works well!
In that context:
Tested-by: Andrew Jeffery
was set. Add a
> property to set or unset this bit. This is useful to test boot images.
>
> For now, only activate this property on the ast2600-evb and rainier-bmc
> machines for which eMMC images are available or can be built.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
attribute first.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> This value is taken from a running Rainier machine.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
v_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
> +if (emmc) {
> +qdev_prop_set_uint8(card, "boot-config", boot_emmc ? 0x48 : 0x0);
0x48 feels a little bit magic. I poked around a bit and there are some
boot-config macros, but not the ones you need and they're all in an
"internal" header anyway. I guess this is fine for now?
Reviewed-by: Andrew Jeffery
port, so return false
> always for these.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
(0x1 << 23)
>
> +/* STRAP1 SCU500 */
> +#define AST2600_HW_STRAP_BOOT_SRC_EMMC(0x1 << 2)
> +#define AST2600_HW_STRAP_BOOT_SRC_SPI (0x0 << 2)
Maybe these should have a `SCU_` prefix for consistency?
Anyway:
Reviewed-by: Andrew Jeffery
flash device is.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> The QEMU device representing the eMMC device of machine is currently
> created with type SD_CARD. Change the type to EMMC now that it is
> available.
>
> Signed-off-by: Cédric Le Goater
On Tue, 2024-07-02 at 18:15 +0200, Philippe Mathieu-Daudé wrote:
> On 2/7/24 07:06, Andrew Jeffery wrote:
> > On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote:
> > > On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote:
> > > > When booting U-boot/Linux on Aspeed
ain problem I had when I
wrote the Linux driver for the Aspeed controller was the phase tuning,
but that doesn't sound related.
Andrew
mething unexpected happened,
> so we should return an error.
>
> Added SBI related return code's defines.
>
> Signed-off-by: Alexei Filippov
> Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit")
> ---
> Changes since v7:
> - Fix
On Fri, 21 Jun 2024 04:48:30 + "Ho-Ren (Jack) Chuang"
wrote:
> If we simply move the set_node_memory_tier() from memory_tier_init() to
> late_initcall(), it will result in HMAT not registering the
> mt_adistance_algorithm callback function,
Immediate reaction: then don't do that!
> because
> #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19
> #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
>
> Signed-off-by: Zheyu Ma
Reviewed-by: Andrew Jeffery
> #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19
> #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
>
> Signed-off-by: Zheyu Ma
Reviewed-by: Andrew Jeffery
> ---
> Changes in v3:
> - Add the reproducer
>
> Changes in v2:
> - Introduce
as we initialise reg_table. I feel
it would help maintain safety in the face of future changes (i.e. if
another reg table were introduced). With that approach the hunk above
can be dropped.
> +
> +if (idx >= reg_table_size) {
This condition would then become:
```
if (idx >= agc->reg_table_size) {
```
Thoughts?
Andrew
Yes, Need to check whether the "offset" exceeds the "size" argument of
gem_receive() in get_queue_from_screen() function;
-邮件原件-
发件人: Peter Maydell
发送时间: 2024年6月6日 20:06
收件人: Edgar E. Iglesias
抄送: andrew Yuan ; luc.mic...@amd.com;
alist...@alistair23.me; jasow
OK，I will send another patch for the missing logic for the DISABLE_MASK bit;
发件人: Edgar E. Iglesias
发送时间: 2024年6月6日 19:04
收件人: andrew Yuan
抄送: luc.mic...@amd.com; alist...@alistair23.me; peter.mayd...@linaro.org;
jasow...@redhat.com; qemu-...@nongnu.org; qemu-devel@nongnu.org
主题: Re: [PATCH
- removed 'gpa' boolean from riscv_iommu_spa_fetch()
>> - 'en_s' is no longer used for early MSI address match
>>
>> - patch 10:
>> - add ATS steps in riscv_iommu_validate_device_ctx()
>> - check for 's->enable_ats' before adding RISCV
27;m not very active wrt qemu these days but am still interested in
Aspeed-related patches. For what it's worth:
Reviewed-by: Andrew Jeffery
> ---
> MAINTAINERS | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 951556224a..0f63bcd
On Thu, May 30, 2024 at 01:05:41PM GMT, Andrew Jones wrote:
> On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> > We need #address-cells properties in all interrupt controllers that are
> > referred by an interrupt-map [1]. For the RISC-V machine, both PLI
On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> We need #address-cells properties in all interrupt controllers that are
> referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and
> APLIC controllers must have this property.
>
> PLIC already sets it in create
On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote:
> Hi Daniel,
> thank you for your help.
>
> I found that only the cover is without many maintainers. I used to send
> patches by git send-email --dry-run --to 'qemu-devel@nongnu.org,
> qemu-ri...@nongnu.org' --cc-cmd='scripts/get_maintainer.p
ve_hw_breakpoint(vaddr addr, vaddr len, int type)
> +{
> +/* TODO; To be implemented later. */
> +return -EINVAL;
> +}
> +
> +void kvm_arch_remove_all_hw_breakpoints(void)
> +{
> +/* TODO; To be implemented later. */
> +}
> +
> +void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
> +{
> +if (kvm_sw_breakpoints_active(cs)) {
> +dbg->control |= KVM_GUESTDBG_ENABLE;
> +}
> +}
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
GET_KVM_HAVE_GUEST_DEBUG=y
> TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
> TARGET_NEED_FDT=y
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
case KVM_EXIT_RISCV_CSR:
> ret = kvm_riscv_handle_csr(cs, run);
> break;
> +case KVM_EXIT_DEBUG:
> +if (kvm_riscv_handle_debug(cs)) {
> +ret = EXCP_DEBUG;
> +}
> +break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
>__func__, run->exit_reason);
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, May 27, 2024 at 02:19:14AM GMT, Chao Du wrote:
> Set the control flag when there are active breakpoints. This will
> help KVM to know the status in the userspace.
>
> Signed-off-by: Chao Du
> ---
> target/riscv/kvm/kvm-cpu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>
On Mon, May 27, 2024 at 02:19:13AM GMT, Chao Du wrote:
> This patch implements insert/remove software breakpoint process:
>
> Add an input parameter for kvm_arch_insert_sw_breakpoint() and
> kvm_arch_remove_sw_breakpoint() to pass the length information,
> which helps us to know whether it is a RV
Add appropriate commit message.
> - Fix error handling according to Andrew Jones suggestion.
> target/riscv/kvm/kvm-cpu.c | 11 +++
> target/riscv/sbi_ecall_interface.h | 12
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
>
On Tue, Mar 12, 2024 at 09:52:21PM GMT, Fei Wu wrote:
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A corresp
On Tue, Mar 12, 2024 at 09:52:20PM GMT, Wu, Fei2 wrote:
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> a virt CPU type (rvsp-ref) as compliant as possible.
We should add the RVA23 profile cpu type
;max_hart_per_socket, BITS_PER_LONG) + 1;
> +} else {
> +hart_bits = 0;
> +}
> +
> ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
> KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
> &hart_bits, true, NULL);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
On Wed, May 15, 2024 at 02:25:31PM GMT, Eric Cheng wrote:
> On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote:
> > From: Tomasz Jeznach
> >
> > Generate device tree entry for riscv-iommu PCI device, along with
> > mapping all PCI device identifiers to the single IOMMU device instance.
> >
> >
On Fri, May 10, 2024 at 06:36:51PM GMT, Frank Chang wrote:
...
> > static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext
> > *ctx,
> > -IOMMUTLBEntry *iotlb)
> > +IOMMUTLBEntry *iotlb, bool gpa)
> > {
> > +dma_addr_t addr, base;
> > +uint64_t satp, gatp, pte;
> >
On Thu, May 09, 2024 at 01:26:56PM GMT, Atish Kumar Patra wrote:
> On Thu, May 2, 2024 at 5:39 AM Andrew Jones wrote:
> >
> > On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 4/29/24 16:28, Atish Patra wrote:
On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 5/8/24 08:22, Andrew Jones wrote:
> > On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote:
> > > This extension has now been ratified:
> > > https://jira.riscv.org/browse/R
ation (Zba_Zbb_Zbs)")
> +MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
> };
>
> static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
> --
> 2.44.0
>
>
Reviewed-by: Andrew Jones
I think we should also either change the false to true for RVB in
misa_ext_cfgs[] or at least ensure RVB is set for the 'max' cpu
type in riscv_init_max_cpu_extensions().
Thanks,
drew
On Fri, May 03, 2024 at 01:39:32PM GMT, Aleksei Filippov wrote:
>
>
> On 25.04.2024 12:21, Andrew Jones wrote:
> > On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> > > On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > > > k
On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 4/29/24 16:28, Atish Patra wrote:
> > Currently, if a counter monitoring cycle/instret is stopped via
> > mcountinhibit we just update the state while the value is saved
> > during the next read. This is not accurate
On April 27, 2024 9:24:04 AM GMT+02:00, Michael Tokarev wrote:
>27.04.2024 09:59, Michael Tokarev wrote:
>> 27.04.2024 09:23, Andrew Jones wrote:
>...
>>> It's possible to cross-compile qemu, so it'd be good to add that to the CI
>>> for riscv until
's reasonable to also pick
it up. I suggest we keep this patch one way or another, though.
Thanks,
drew
>
>Thanks,
>
>/mjt
>
>
>> Reviewed-by: Andrew Jones
>> Signed-off-by: Yong-Xuan Wang
>>
>> ---
>> Changelog
>> v2:
>>
t. There's no change in boot time if the guest isn't
> using earlycon.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 111 +++++
> target/riscv/sbi_ecall_interface.h | 17 +
> 2 files changed, 128 insertions(+)
>
Reviewed-by: Andrew Jones
gt; The case we're handling happens with an EINVAL error code. If we fail to
> disable the extension in KVM for any other reason, error out.
>
> We'll also keep erroring out when we fail to enable an extension in KVM,
> since adding the extension in riscv,isa at this point w
On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new e
On Wed, Apr 24, 2024 at 04:28:09PM +0200, Andrew Jones wrote:
> Implementing wrs.nto to always just return is consistent with the
> specification, as the instruction is permitted to terminate the
> stall for any reason, but it's not useful for virtualization, where
> we'd lik
n-specific.
Signed-off-by: Andrew Jones
Reviewed-by: Christoph Müllner
---
v3:
- Sending again, hoping the ü remains in Müllner
v2:
- Added #ifndef CONFIG_USER_ONLY around helper call
target/riscv/helper.h | 1 +
target/riscv/insn_trans/trans_rvzawrs.
On Mon, Apr 22, 2024 at 11:08:31AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 4/22/24 10:43, Andrew Jones wrote:
> > On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote:
> > > Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
Hello, everyone.
Was added missed "trace.h"
Best regards.
On Mon, Apr 22, 2024 at 5:17 PM Andrew Melnychenko wrote:
>
> There was an issue with Qemu build with "--disable-system".
> The traces could be generated and the build fails.
> The traces were 'cut o
There was an issue with Qemu build with "--disable-system".
The traces could be generated and the build fails.
The traces were 'cut out' for previous patches, and overall,
the 'system' source set should be used like in pre-'eBPF blob' patches.
Sign
Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones
---
target/riscv/cpu
on't
try to use any extensions which aren't in the ISA string. So, disabling
these types of extensions either shouldn't generally be done (so a noisy
warning helps prohibit that) or done for debug purposes (where a noisy
warning is fine).
>
> Suggested-by: Andrew Jones
>
On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not
> trigger qemu abort with vendor-specific sbi.
>
> Add new error path to provide proper error in case of
> qemu_chr_fe_read_all() may not return sizeof(ch).
I thin
On Mon, Apr 22, 2024 at 01:55:31PM +1000, Alistair Francis wrote:
> On Sat, Apr 13, 2024 at 9:26 PM Alexei Filippov
> wrote:
> >
> > kvm_riscv_handle_sbi() may return not supported return code to not trigger
> > qemu abort with vendor-specific sbi.
> >
> > Added SBI related return code's defines.
s: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit")
> ---
>
> Changes since v3:
> -Clear Reviewed-by tags
> target/riscv/kvm/kvm-cpu.c | 13 +
> target/riscv/sbi_ecall_interface.h | 12
> 2 files changed, 17 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones
On Tue, 9 Apr 2024 12:00:06 -0700 "Ho-Ren (Jack) Chuang"
wrote:
> Hi Jonathan,
>
> On Fri, Apr 5, 2024 at 6:56 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 00:07:05 +
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> > > Since different memory devices require finding, allocating, and pu
There was an issue with Qemu build with "--disable-system".
The traces could be generated and the build fails.
The traces were 'cut out' for previous patches, and overall,
the 'system' source set should be used like in pre-'eBPF blob' patches.
Sign
Hi all,
I've reviewed and checked - this patch is necessary!
Acked-by: and...@daynix.com
On Thu, Mar 28, 2024 at 11:39 AM Yuri Benditovich
wrote:
>
> Hi Andrew,
> Can you please check the indirection table copy and ack on the patch
> if the fix is correct
>
> Thanks,
&g
On Mon, Mar 25, 2024 at 04:01:16PM +0300, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not trigger
> qemu abort with vendor-specific sbi.
>
> Added SBI related return code's defines.
>
> Signed-off-by: Alexei Filippov
> Fixes: 4eb47125 ("target/riscv: H
1 - 100 of 1149 matches
Mail list logo
