On 2/24/08, claude vittoria [EMAIL PROTECTED] wrote:
So in qemu I don't get the same comportement. The add of lr = pc + 4
gives lr = pc + 8 into qemu.
I think that s-pc += 4 at start of disas_arm_insn alters the result.
Could you confirm ?
0x7caddlr, pc, #4
0x80ldrpc
Hello,
I got a problem in an IRQ handler of mutek OS
(https://www-asim.lip6.fr/trac/mutekh), target ARM Integrator/CM
922T-XA10. I try to port it on Qemu. A porting has been done for Skyeyes
So in qemu I don't get the same comportement. The add of lr = pc + 4
gives lr = pc + 8 into qemu.
I
Hi,
I test the PPC fpu with machar test
(http://orion.math.iastate.edu/burkardt/c_src/machar/machar.html).
I get an error with qemu-cvs :
invalid bits: 0042 for opcode: 13 - 01 - 01 (4fdef042) 00037e60
ASM code :
00037e54 __isnan:
37e54: fc 00 04 8e mffsf0
37e58:
:52 +0100, claude vittoria wrote:
Hi everybody,
I think that I get a wrong result with mtfsfi instruction.
I think to get a solution, see below.
Could you confirm my opinion ?
Seems there have been (once again) a confusion between IBM bit notation
(0 is MSB...) and standard one. You're right
Hi everybody,
I think that I get a wrong result with mtfsfi instruction.
I think to get a solution, see below.
Could you confirm my opinion ?
Thanks,
Claude
translate.c
l344:EXTRACT_HELPER(crbD, 21, 5);
...
l375:EXTRACT_HELPER(FPIMM, 20, 4); ==FPIMM must be (FPIMM, 12, 4) or crbB
1 for
