Re: [PATCH] linux-user: Fix loading of BSS segments

Laurent Vivier wrote: > If this patch fixes also your problem I will take this one instead. Awesome, I can confirm that this patch fixes my problem. Thanks, Stephen

Re: [PATCH] linux-user: Fix loading of BSS segments

Laurent Vivier wrote: > Is this also fixing what "linux-user/elfload: Fix handling of pure BSS > segments" [1] patch fixes? I can do a v2 of my patch with a better commit description and addressing Peter's questions, but feel free to take this patch instead. It has a much clearer commit msg and

Re: [PATCH] linux-user/elfload: Fix handling of pure BSS segments

Alex Bennee writes: > Hmm I tried the following patch but evidently there is more to be done > to convince it: > collect2: fatal error: cannot find 'ld' Oh, I'm using ld.lld-10. aarch64-linux-gnu-gcc -B/usr/lib/llvm-10/bin works for me. You'll have to get the necessary packages for lld-10 and p

Re: [PATCH] linux-user/elfload: Fix handling of pure BSS segments

Alex Bennee writes: >> Apologies for the unclear commit msg. I was also seeing a SIGSEGV in >> zero_bss() with the binaries I was generating. I was using LLD to generate >> the binaries. The binaries all had LOAD segments with a file size of >> 0. > > How hairy is the generation of these binaries

Re: Re: [PATCH] linux-user/elfload: Fix handling of pure BSS segments

Hi Peter, > (a) what does "fails to load" mean here? In the sample binary > I had, we got a SIGSEGV in zero_bss() when it tried to memset() > memory that hadn't been mmap()ed. Is that the only failure mode, > or can this manifest in other ways too? Apologies for the unclear commit msg. I was als

[PATCH] linux-user/elfload: Fix handling of pure BSS segments

qemu-user fails to load ELFs with only BSS and no data section Signed-off-by: Ben Hutchings Signed-off-by: Stephen Long --- Submitting this on behalf of Ben Hutchings. Feel free to edit the commit msg. linux-user/elfload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

Re: [PATCH v3 00/81] target/arm: Implement SVE2

Hi Richard, Apologies for forgetting to cc you in the previous reply. What's the plan to get this patch series into master? Thanks, Stephen

Re: [PATCH v3 00/81] target/arm: Implement SVE2

Hi Richard, what's the plan to get this patch series into master? Thanks, Stephen

Re: linux-user/elfload.c: Seeing a segfault in qemu with a binary with no data section

Ahh whoops, I see the actual intended change was to replace "eppnt->p_filesz != 0" with "vaddr_len != 0", which isn't on master. Thanks, Stephen

Re: linux-user/elfload.c: Seeing a segfault in qemu with a binary with no data section

I think that a variant of that patch made it into master: /* * Some segments may be completely empty without any backing file * segment, in that case just let zero_bss allocate an empty buffer * for it. */ if (eppnt->p_fil

linux-user/elfload.c: Seeing a segfault in qemu with a binary with no data section

Hi, we are seeing a segfault in qemu in the following code snippet in zero_bss(): if (host_start < host_map_start) { memset((void *)host_start, 0, host_map_start - host_start); } The elf doesn't have a data section, so host_start isn't mapped. I'm not sure whether this is a qemu issue or the

Re: Re: [PATCH] Fix stack smashing when handling PR_GET_PDEATHSIG

>> linux-user/syscall.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/linux-user/syscall.c b/linux-user/syscall.c >> index 05f0391..91f9114 100644 >> --- a/linux-user/syscall.c >> +++ b/linux-user/syscall.c >> @@ -10256,7 +10256,7 @@ static abi_long do_syscall1(void

[PATCH v2] tcg: Fix tcg gen for vectorized absolute value

Signed-off-by: Stephen Long --- tcg/tcg-op-gvec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) Whoops, I forgot to add the signed off line. diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 3707c0effb..793d4ba64c 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c

[PATCH] tcg: Fix tcg gen for vectorized absolute value

--- tcg/tcg-op-gvec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) qemu was generating buggy tcg for arm64's vectorized absolute value insn when the machine didn't support avx insns. Subtracting a mask of -1 for each negative element doesn't add 1 to each negative element. For exam

[RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops

Signed-off-by: Stephen Long --- sve2.risu | 14 ++ 1 file changed, 14 insertions(+) diff --git a/sve2.risu b/sve2.risu index 44f227e..d0ad7c9 100755 --- a/sve2.risu +++ b/sve2.risu @@ -480,3 +480,17 @@ WHILEHS A64_V00100101 size:2 1 rm:5 000 sf:1 10 rn:5 0 pd:4 ## pointer

[RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns

Signed-off-by: Stephen Long --- sve2.risu | 8 1 file changed, 8 insertions(+) diff --git a/sve2.risu b/sve2.risu index 84ae527..00ac186 100755 --- a/sve2.risu +++ b/sve2.risu @@ -514,3 +514,11 @@ LDNT1SW_64 A64_V1100010 10 00 rm:5 100 pg:3 zn:5 zt:5 LDNT1W_64 A64_V1100010

[RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations

Signed-off-by: Stephen Long --- sve2.risu | 12 1 file changed, 12 insertions(+) diff --git a/sve2.risu b/sve2.risu index 725bbd2..6177848 100755 --- a/sve2.risu +++ b/sve2.risu @@ -272,6 +272,18 @@ HISTSEG A64_V01000101 size:2 1 zm:5 101000 zn:5 zd:5 \ HISTCNT A64_V

[RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated)

Signed-off-by: Stephen Long --- sve2.risu | 7 +++ 1 file changed, 7 insertions(+) diff --git a/sve2.risu b/sve2.risu index 313c5ac..48b2957 100755 --- a/sve2.risu +++ b/sve2.risu @@ -315,6 +315,13 @@ FCVTLT_HS A64_V01100100 10 0010 01 101 pg:3 zn:5 zd:5 FCVTNT_DS A64_V01100100

[RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops

Signed-off-by: Stephen Long --- sve2.risu | 10 ++ 1 file changed, 10 insertions(+) diff --git a/sve2.risu b/sve2.risu index 7f70bfa..44f227e 100755 --- a/sve2.risu +++ b/sve2.risu @@ -470,3 +470,13 @@ FMINP A64_V01100100 size:2 010 111 100 pg:3 zm:5 zdn:5 \ # Table Lookup

[RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 51 +++ 1 file changed, 51 insertions(+) diff --git a/sve2.risu b/sve2.risu index 346b812..f2e4dba 100755 --- a/sve2.risu +++ b/sve2.risu @@ -11,6 +11,57 @@ PMULA64_V0100 00 1 zm:5 0110

[RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns

Signed-off-by: Stephen Long --- sve2.risu | 20 1 file changed, 20 insertions(+) diff --git a/sve2.risu b/sve2.risu index d0ad7c9..84ae527 100755 --- a/sve2.risu +++ b/sve2.risu @@ -494,3 +494,23 @@ FMLALB_vec A64_V011001001 01 zm:5 100 000 zn:5 zda:5 FMLALT_vec

[RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops

Signed-off-by: Stephen Long --- sve2.risu | 14 ++ 1 file changed, 14 insertions(+) create mode 100755 sve2.risu diff --git a/sve2.risu b/sve2.risu new file mode 100755 index 000..78debd9 --- /dev/null +++ b/sve2.risu @@ -0,0 +1,14 @@ +# Input file for risugen defining AArch64

[RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops

Signed-off-by: Stephen Long --- sve2.risu | 86 +++ 1 file changed, 86 insertions(+) diff --git a/sve2.risu b/sve2.risu index 8602059..1bcbd93 100755 --- a/sve2.risu +++ b/sve2.risu @@ -66,6 +66,92 @@ SQDMLSLTA64_V01000100 size:2 0 zm

[RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 10 ++ 1 file changed, 10 insertions(+) diff --git a/sve2.risu b/sve2.risu index 78debd9..346b812 100755 --- a/sve2.risu +++ b/sve2.risu @@ -1,6 +1,16 @@ # Input file for risugen defining AArch64 SVE2 instructions .mode arm.aarch64

[RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 41 + 1 file changed, 41 insertions(+) diff --git a/sve2.risu b/sve2.risu index c48717b..8602059 100755 --- a/sve2.risu +++ b/sve2.risu @@ -25,6 +25,47 @@ URSHR A64_V0100 tszh:2 00 1101 100 pg:3

[RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns

Signed-off-by: Stephen Long --- sve2.risu | 7 +++ 1 file changed, 7 insertions(+) diff --git a/sve2.risu b/sve2.risu index adc5dd1..4b2a79d 100755 --- a/sve2.risu +++ b/sve2.risu @@ -297,6 +297,13 @@ SM4EA64_V01000101 00 10001 1 11100 0 zm:5 zdn:5 SM4EKEY A64_V01000101

[RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops

Signed-off-by: Stephen Long --- sve2.risu | 25 + 1 file changed, 25 insertions(+) diff --git a/sve2.risu b/sve2.risu index 50ff756..ca14193 100755 --- a/sve2.risu +++ b/sve2.risu @@ -123,6 +123,31 @@ UMULLB A64_V01000101 size:2 0 zm:5 011 110 zn:5 zd:5

[RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops

Signed-off-by: Stephen Long --- sve2.risu | 6 ++ 1 file changed, 6 insertions(+) diff --git a/sve2.risu b/sve2.risu index 1bcbd93..7f70bfa 100755 --- a/sve2.risu +++ b/sve2.risu @@ -1,6 +1,12 @@ # Input file for risugen defining AArch64 SVE2 instructions .mode arm.aarch64 +# Permute

[RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 13 + 1 file changed, 13 insertions(+) diff --git a/sve2.risu b/sve2.risu index 6177848..adc5dd1 100755 --- a/sve2.risu +++ b/sve2.risu @@ -1,6 +1,19 @@ # Input file for risugen defining AArch64 SVE2 instructions .mode arm.aarch64

[RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns

Signed-off-by: Stephen Long --- sve2.risu | 4 1 file changed, 4 insertions(+) diff --git a/sve2.risu b/sve2.risu index 48b2957..c48717b 100755 --- a/sve2.risu +++ b/sve2.risu @@ -333,3 +333,7 @@ FMAXP A64_V01100100 size:2 010 110 100 pg:3 zm:5 zdn:5 \ !constraints { $size != 0

[RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 11 +++ 1 file changed, 11 insertions(+) diff --git a/sve2.risu b/sve2.risu index 4b2a79d..313c5ac 100755 --- a/sve2.risu +++ b/sve2.risu @@ -1,6 +1,17 @@ # Input file for risugen defining AArch64 SVE2 instructions .mode arm.aarch64

[RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops

Signed-off-by: Stephen Long --- sve2.risu | 6 ++ 1 file changed, 6 insertions(+) diff --git a/sve2.risu b/sve2.risu index 5bd515c..725bbd2 100755 --- a/sve2.risu +++ b/sve2.risu @@ -266,6 +266,12 @@ MATCH A64_V01000101 size:2 1 zm:5 100 pg:3 zn:5 0 pd:4 \ NMATCH A64_V

[RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns

Signed-off-by: Stephen Long --- sve2.risu | 6 ++ 1 file changed, 6 insertions(+) diff --git a/sve2.risu b/sve2.risu index 1ebb08c..5bd515c 100755 --- a/sve2.risu +++ b/sve2.risu @@ -260,6 +260,12 @@ RSUBHNB A64_V01000101 size:2 1 zm:5 011 110 zn:5 zd:5 \ RSUBHNT A64_V

[RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops

Signed-off-by: Stephen Long --- sve2.risu | 76 +++ 1 file changed, 76 insertions(+) diff --git a/sve2.risu b/sve2.risu index caca5c0..1ebb08c 100755 --- a/sve2.risu +++ b/sve2.risu @@ -184,6 +184,82 @@ SLI A64_V01000101 tszh:2 0

[RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions

Added risu patterns for all the sve2 instructions. Please point all any glaring mistakes. Stephen Long (22): sve2.risu: Add patterns for floating-point pairwise ops sve2.risu: Add patterns for integer multiply (unpredicated) ops sve2.risu: Add patterns for integer (predicated) ops sve2

[RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops

Signed-off-by: Stephen Long --- sve2.risu | 36 1 file changed, 36 insertions(+) diff --git a/sve2.risu b/sve2.risu index ca14193..caca5c0 100755 --- a/sve2.risu +++ b/sve2.risu @@ -148,6 +148,42 @@ BEXTA64_V01000101 size:2 0 zm:5 1011 00 zn:5

[RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops

Signed-off-by: Stephen Long --- sve2.risu | 61 +++ 1 file changed, 61 insertions(+) diff --git a/sve2.risu b/sve2.risu index f2e4dba..50ff756 100755 --- a/sve2.risu +++ b/sve2.risu @@ -62,6 +62,67 @@ USQADD A64_V01000100 size:2 011

[PATCH RISU 4/4] sve2.risu: Add patterns for widening integer arithmetic

Signed-off-by: Stephen Long --- sve2.risu | 62 +++ 1 file changed, 62 insertions(+) diff --git a/sve2.risu b/sve2.risu index 9e48e1e..a4d5312 100755 --- a/sve2.risu +++ b/sve2.risu @@ -67,6 +67,68 @@ USQADD A64_V01000100 size:2 011

[PATCH RISU 2/4] sve2.risu: Add patterns for integer multiply (unpredicated)

Signed-off-by: Stephen Long --- sve2.risu | 11 +++ 1 file changed, 11 insertions(+) diff --git a/sve2.risu b/sve2.risu index eb1d75a..ccdb19f 100755 --- a/sve2.risu +++ b/sve2.risu @@ -1,6 +1,17 @@ # Input file for risugen defining AArch64 SVE2 instructions .mode arm.aarch64

[PATCH RISU 3/4] sve2.risu: Add patterns for integer (predicated) ops

Signed-off-by: Stephen Long --- sve2.risu | 55 +++ 1 file changed, 55 insertions(+) diff --git a/sve2.risu b/sve2.risu index ccdb19f..9e48e1e 100755 --- a/sve2.risu +++ b/sve2.risu @@ -12,6 +12,61 @@ PMULA64_V0100 size:2 1 zm

[PATCH RISU 1/4] sve2.risu: Add patterns for floating-point pairwise ops

Signed-off-by: Stephen Long --- sve2.risu | 14 ++ 1 file changed, 14 insertions(+) create mode 100755 sve2.risu diff --git a/sve2.risu b/sve2.risu new file mode 100755 index 000..eb1d75a --- /dev/null +++ b/sve2.risu @@ -0,0 +1,14 @@ +# Input file for risugen defining AArch64

[PATCH RISU 0/4] Add patterns for SVE2

ending these to the mailing list. This version of the patch series includes one more patch. Stephen Long (4): sve2.risu: Add patterns for floating-point pairwise ops sve2.risu: Add patterns for integer multiply (unpredicated) sve2.risu: Add patterns for integer (predicated) ops sve2.risu: A

[PATCH v2] Fix stack smashing when handling PR_GET_PDEATHSIG

The bug was triggered by the following code on aarch64-linux-user: #include #include int main(void) { int PDeathSig = 0; if (prctl(PR_GET_PDEATHSIG, &PDeathSig) == 0 && PDeathSig == SIGKILL) prctl(PR_GET_PDEATHSIG, 0); return (PDeathSig == SIGKILL); } Signed-off-by:

[PATCH] Fix stack corruption when handling PR_GETDEATHSIG

From: Ana Pazos Signed-off-by: Ana Pazos --- Submitting this patch on behalf of Ana Pazos. The bug was triggered by the following c file on aarch64-linux-user. > #include > #include > > int main() { > int PDeachSig = 0; > if (prctl(PR_GET_PDEATHSIG, &PDeachSig) == 0 && PDeachSig == SIGKIL

[PATCH] target/arm: Implement SVE2 fp multiply-add long

Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 12 ++ target/arm/sve_helper.c| 76 + target/arm/translate-sve.c | 86

[PATCH RFC] target/arm: Implement SVE2 fp multiply-add long

Implements FMLALB, FMLALT, FMLSLB, FMLSLT Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 5 target/arm/sve.decode | 6 target/arm/sve_helper.c| 27 ++ target/arm/translate-sve.c | 58 ++ 4 files changed, 96

[PATCH RFC v2] target/arm: Implement SVE2 bitwise shift immediate

Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Signed-off-by: Stephen Long --- Made the changes Richard requested. I think the only SVE2 insns left are the FMLA and FMLS (both vector and indexed) ones. There are a couple of patches that Richard has to review: * this one * TBX / TBL (not fully

[PATCH RFC v2] target/arm: Implement SVE2 FLOGB

Signed-off-by: Stephen Long --- I made the changes Richard requested. I took out the status field for the helper function. include/fpu/softfloat.h| 5 +++ target/arm/helper-sve.h| 4 +++ target/arm/sve.decode | 4 +++ target/arm/sve_helper.c| 63

[PATCH RFC] target/arm: Implement SVE2 FLOGB

Signed-off-by: Stephen Long --- Right now, there is no log2 function for half precision floats, so I'm not sure how to proceed. Currently, I just added a TODO comment. target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 3 +++ targe

[PATCH RFC] target/arm: Implement SVE2 bitwise shift immediate

Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Signed-off-by: Stephen Long --- I'm not too sure about the casting I'm doing willy nilly in the helper functions, but I think they should be ok. Also, there might be some avenues for optimization when translating similar to asr_zpzi an

[PATCH v2] target/arm: Implement SVE2 fp convert precision

Implements FCVTLT, FCVTX, FCVTNT, FCVTXNT Signed-off-by: Stephen Long --- Fixed a compilation error and collapsed the translation functions with a macro. > Ignore my previous patchset. I missed the insn FCVTX and I ended up > squashing those commits into this one. At the moment, I'm

[PATCH] target/arm: Implement SVE2 fp convert precision

Implements FCVTLT, FCVTX, FCVTNT, FCVTXNT Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 15 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 59 ++ target/arm/translate-sve.c | 48

[PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c| 7 +++ target/arm/translate-sve.c | 8 4 files changed, 18 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 27a8cc2cbe

[PATCH RFC 1/3] target/arm: Implement SVE2 FCVTNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 4 target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 16 4 files changed, 45 insertions(+) diff --git a/target/arm/helper-sve.h b/target

[PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion

The only insn left in this category is BFCVTNT. I couldn't find any helper functions for bfloats so I'm not sure how to approach this insn. Also, for insn FCVTXNT, I'm not sure if it is ok to set the status rounding mode to odd like that. Stephen Long (3): target/arm: Implem

[PATCH RFC 2/3] target/arm: Implement SVE2 FCVTLT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 23 +++ target/arm/translate-sve.c | 16 4 files changed, 46 insertions(+) diff --git a/target/arm/helper-sve.h b/target

[PATCH RFC v2] target/arm: Implement SVE2 TBL, TBX

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 10 ++ target/arm/internals.h | 12 +++ target/arm/sve.decode | 5 +++ target/arm/sve_helper.c| 71 ++ target/arm/translate-sve.c | 20 +++ 5 files changed, 112

[PATCH RFC v3 1/3] target/arm: Implement SVE2 AESMC, AESIMC

Signed-off-by: Stephen Long --- target/arm/crypto_helper.c | 36 +--- target/arm/sve.decode | 10 ++ target/arm/translate-sve.c | 20 3 files changed, 51 insertions(+), 15 deletions(-) diff --git a/target/arm/crypto_helper.c b

[PATCH RFC v3 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1

Signed-off-by: Stephen Long --- target/arm/crypto_helper.c | 12 target/arm/helper-sve.h| 1 + target/arm/helper.h| 2 ++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 8 target/arm/translate-sve.c | 30 ++ 6

[PATCH RFC v3 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E

Signed-off-by: Stephen Long --- target/arm/cpu.h | 5 + target/arm/crypto_helper.c | 38 ++ target/arm/helper-sve.h| 2 ++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 8 target/arm/translate-sve.c | 14

[PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions

ephen Long (3): target/arm: Implement SVE2 AESMC, AESIMC target/arm: Implement SVE2 AESE, AESD, SM4E target/arm: Implement SVE2 SM4EKEY, RAX1 target/arm/cpu.h | 5 +++ target/arm/crypto_helper.c | 86 -- target/arm/helper-sve.h| 3 ++ targe

[PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 30 ++ 4 files changed, 57 insertions(+) diff --git a/target/arm/helper-sve.h

[PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 10 ++ target/arm/sve_helper.c| 15 +++ target/arm/translate-sve.c | 18 ++ 4 files changed, 46 insertions(+) diff --git a/target/arm/helper-sve.h b/target

[PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions

Used one macro to cover the helper functions for SVE2 AESC, AESIMC, AESE, AESD. No macro was used to implement the helper functions for SM4E, SM4EKEY, RAX1. Stephen Long (3): target/arm: Implement SVE2 AESMC, AESIMC target/arm: Implement SVE2 AESE, AESD, SM4E target/arm: Implement SVE2

[PATCH RFC v2 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E

Signed-off-by: Stephen Long --- target/arm/cpu.h | 5 + target/arm/helper-sve.h| 4 target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 11 +++ target/arm/translate-sve.c | 16 5 files changed, 42 insertions(+) diff --git a

RE: [PATCH RFC] target/arm: Implement SVE2 TBL, TBX

Oh, maybe I misread the manual description for SVE2 TBL, but I thought Zm was the indexes register and the loop compares the index from Zm with the total number of elems, table_elems. -Original Message- From: Richard Henderson Sent: Friday, April 24, 2020 2:37 PM To: Stephen Long

[PATCH RFC 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E

Signed-off-by: Stephen Long --- target/arm/cpu.h | 5 + target/arm/helper-sve.h| 4 target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 25 + target/arm/translate-sve.c | 16 5 files changed, 56 insertions

[PATCH RFC 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 21 + target/arm/translate-sve.c | 30 ++ 4 files changed, 58 insertions(+) diff --git a/target/arm/helper

[PATCH RFC 0/3] target/arm: Implement SVE2 Crypto Extensions

Used the helper functions in crypto_helper.c to implement the helper functions for the crypto insns. Stephen Long (3): target/arm: Implement SVE2 AESMC, AESIMC target/arm: Implement SVE2 AESE, AESD, SM4E target/arm: Implement SVE2 SM4EKEY, RAX1 target/arm/cpu.h | 5 +++ target

[PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 10 ++ target/arm/sve_helper.c| 13 + target/arm/translate-sve.c | 18 ++ 4 files changed, 44 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm

[PATCH RFC] target/arm: Implement SVE2 SPLICE, EXT

Signed-off-by: Stephen Long I'm not sure I can just use the SVE helper functions for the SVE2 variants of EXT and SPLICE. --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 39 +- 2 files changed, 42 insertions(+), 5 deletions(-)

[PATCH RFC] target/arm: Implement SVE2 TBL, TBX

Signed-off-by: Stephen Long These insns don't show up under any SVE2 categories in the manual. But if you lookup each insn, you'll find they have SVE2 variants. --- target/arm/helper-sve.h| 10 +++ target/arm/sve.decode | 5 target/arm/sve_helper

[PATCH v3] target/arm: Implement SVE2 FMMLA

Signed-off-by: Stephen Long Fixed the errors Richard pointed out. --- target/arm/cpu.h | 10 + target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 42 ++ target/arm/translate-sve.c | 29

[PATCH RFC] target/arm: Implement SVE2 gather load insns

(vector plus scalar) * LDNT1W (vector plus scalar) Signed-off-by: Stephen Long I'm not sure I'm initializing xs correctly. This also goes for the scatter store insns in the previous patch. --- target/arm/sve.decode | 11 +++ target/arm/translate-sve.c | 8 2 fil

[PATCH v2] target/arm: Implement SVE2 scatter store insns

scalar) Signed-off-by: Stephen Long Cool, it seemed to typedef correctly. --- target/arm/sve.decode | 10 ++ target/arm/translate-sve.c | 8 2 files changed, 18 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index dd987da648..ef5dd281a6 100644 --- a

[PATCH v2] target/arm: Implement SVE2 FMMLA

Signed-off-by: Stephen Long I'm guessing endianness doesn't matter because we are writing to the corresponding 32-bit/64-bit in the destination register. --- target/arm/cpu.h | 10 + target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4

[PATCH] target/arm: Implement SVE2 scatter store insns

scalar) Signed-off-by: Stephen Long I'm not sure if this is the correct way to do this. --- target/arm/sve.decode | 10 ++ target/arm/translate-sve.c | 28 2 files changed, 38 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode

[PATCH] target/arm: Implement SVE2 FMMLA

ned-off-by: Stephen Long --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 4 target/arm/sve_helper.c| 35 +++ target/arm/translate-sve.c | 29 + 5 files changed, 81

[PATCH 4/4] target/arm: Implement SVE2 RSUBHNB, RSUBHNT

This completes the section 'SVE2 integer add/subtract narrow high part' Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 2 ++ 4 files changed, 22

[PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 3 +++ 4 files changed, 23 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index

[PATCH 0/4] target/arm: Implement last SVE2 narrowing section

Submitting patches for the section 'SVE2 integer add/subtract narrow high part' for early review. Stephen Long (4): target/arm: Implement SVE2 ADDHNB, ADDHNT target/arm: Implement SVE2 RADDHNB, RADDHNT target/arm: Implement SVE2 SUBHNB, SUBHNT target/arm: Implement SVE2 RSUBHN

[PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c | 2 ++ 4 files changed, 22 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index

[PATCH 1/4] target/arm: Implement SVE2 ADDHNB, ADDHNT

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 36 target/arm/translate-sve.c | 13 + 4 files changed, 62 insertions(+) diff --git a/target/arm/helper

[PATCH RFC v5] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Made the fixes Richard noted. target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 +++ target/arm/sve_helper.c| 104 + target/arm/translate-sve.c | 29 +++ 4 files changed, 146 insertions

[PATCH RFC v4] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Fix error in the helper function for HISTSEG target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 +++ target/arm/sve_helper.c| 94 ++ target/arm/translate-sve.c | 29 4 files changed, 136

[PATCH RFC v3] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Disregard my previous patch. There was a mistake in translate_HISTCNT(). target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 +++ target/arm/sve_helper.c| 90 ++ target/arm/translate-sve.c | 29

[PATCH RFC v2] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Whoops, I was mistaken on what HISTSEG was doing. target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 +++ target/arm/sve_helper.c| 90 ++ target/arm/translate-sve.c | 29 4 files changed, 132

[PATCH RFC v2] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Realized that I was handling the predicate register incorrectly for the 32 bit case for histcnt_s. There might be a cleaner way to write the handler function. target/arm/helper-sve.h| 7 target/arm/sve.decode | 6 target/arm/sve_helper.c

[PATCH RFC] target/arm: Implement SVE2 HISTCNT, HISTSEG

Signed-off-by: Stephen Long --- Submitting patch for early review. We can probably lookup two elements at a time for the 32 bit case for histcnt_s. target/arm/helper-sve.h| 7 + target/arm/sve.decode | 6 target/arm/sve_helper.c| 63

[PATCH v4] target/arm: Implement SVE2 MATCH, NMATCH

Signed-off-by: Stephen Long --- Whoops, forgot to complete the comment for do_match2() target/arm/helper-sve.h| 10 +++ target/arm/sve.decode | 5 target/arm/sve_helper.c| 59 ++ target/arm/translate-sve.c | 22 ++ 4 files

[PATCH RFC v3] target/arm: Implement SVE2 MATCH, NMATCH

Signed-off-by: Stephen Long --- Fixed the patch with the suggestions Richard made. I'll be working on the HIST insns next instead of the 'SVE2 integer add/subtract narrow high part' ones. target/arm/helper-sve.h| 10 +++ target/arm/sve.decode | 5 target/a

[PATCH RFC v2] target/arm: Implement SVE2 MATCH, NMATCH

Signed-off-by: Stephen Long --- target/arm/helper-sve.h| 10 target/arm/sve.decode | 5 target/arm/sve_helper.c| 51 ++ target/arm/translate-sve.c | 22 4 files changed, 88 insertions(+) diff --git a/target/arm

[PATCH RFC] target/arm: Implement SVE2 MATCH, NMATCH

Signed-off-by: Stephen Long --- Submitting this for early review. I'm working with Richard on SVE2 support for qemu. I'll be attempting to tackle the insns in the 'SVE2 integer add/subtract narrow high part' category next [1]. [1] ISA manual: https://static.do

Re: [Qemu-devel] [PATCH 0/7] x86: Rework KVM-defaults compat code, enable kvm_pv_unhalt by default

On 10/13/2017 03:01 PM, Eduardo Habkost wrote: > On Wed, Oct 11, 2017 at 04:19:38PM -0400, Waiman Long wrote: >> On 10/10/2017 03:41 PM, Eduardo Habkost wrote: >>> On Tue, Oct 10, 2017 at 02:07:25PM -0400, Waiman Long wrote: >>>> On 10/10/2017 11:50 AM, Eduardo Habko

Re: [Qemu-devel] [PATCH 0/7] x86: Rework KVM-defaults compat code, enable kvm_pv_unhalt by default

On 10/10/2017 03:41 PM, Eduardo Habkost wrote: > On Tue, Oct 10, 2017 at 02:07:25PM -0400, Waiman Long wrote: >> On 10/10/2017 11:50 AM, Eduardo Habkost wrote: >>>> Yes. Another possibility is to enable it when there is >1 NUMA node in >>>> the guest. We gener

Re: [Qemu-devel] [PATCH 0/7] x86: Rework KVM-defaults compat code, enable kvm_pv_unhalt by default

On 10/10/2017 11:50 AM, Eduardo Habkost wrote: >> Yes. Another possibility is to enable it when there is >1 NUMA node in >> the guest. We generally don't do this kind of magic but higher layers >> (oVirt/OpenStack) do. > Can't the guest make this decision, instead of the host? By guest, do you m

Re: [Qemu-devel] [PATCH 0/7] x86: Rework KVM-defaults compat code, enable kvm_pv_unhalt by default

On 10/09/2017 09:39 AM, Paolo Bonzini wrote: > On 06/10/2017 23:52, Eduardo Habkost wrote: >> This series enables kvm_pv_unhalt by default on pc-*-2.11 and >> newer. >> >> To do that, I first reworked the existing >> x86_cpu_change_kvm_default() logic to use compat_props instead, >> so we don't nee

Re: [Qemu-devel] [PATCH v4 13/18] crypto: cipher: add afalg-backend cipher support

2017-07-11 20:29 GMT+08:00 Daniel P. Berrange : > On Tue, Jul 04, 2017 at 04:57:05PM +0800, Longpeng(Mike) wrote: >> Adds afalg-backend cipher support: introduces some private APIs >> firstly, and then intergrates them into qcrypto_cipher_afalg_driver. >> >> Signed-off-by: Longpeng(Mike) >> --- >>

Re: [Qemu-devel] [PATCH v4 12/18] crypto: introduce some common functions for af_alg backend

2017-07-11 20:28 GMT+08:00 Daniel P. Berrange : > On Tue, Jul 04, 2017 at 04:57:04PM +0800, Longpeng(Mike) wrote: >> The AF_ALG socket family is the userspace interface for linux >> crypto API, this patch adds af_alg family support and some common >> functions for af_alg backend. It'll be used by a

Re: [Qemu-devel] [PATCH v4 1/3] qmp: fix object-add assert() without props

On 2016/9/29 下午11:23, Markus Armbruster wrote: Xiao Long Jiang writes: Hi, I have tested this patch on arch s390 system. It works fine. :-) May I credit your help by adding Tested-by: Xiao Long Jiang to the commit message? Just back from holiday. It would be great if you add

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