Re: [Qemu-devel] [PATCH for-2.12?] m25p80: Correct the at25128a/at25256a eeproms size

W dniu 15.04.2018 o 22:31, Philippe Mathieu-Daudé pisze: >From the datasheet (3368J–SEEPR) description: The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. However

Re: [Qemu-devel] [PATCH] m25p80: prevent buffer overflow during erasing

W dniu 15.01.2018 o 16:13, Aleksey Kuleshov pisze: memset is not checked, so it's possible to go beyond the storage. Add checks and truncate requested length. Signed-off-by: Aleksey Kuleshov Acked-by: Marcin Krzemiński --- hw/block/m25p80.c |

Re: [Qemu-devel] [PATCH v7 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

2017 17:18, "mar.krzeminski" <mar.krzemin...@gmail.com <mailto:mar.krzemin...@gmail.com>> wrote: W dniu 03.11.2017 o 01:00, Francisco Iglesias pisze: Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is de

Re: [Qemu-devel] [PATCH v7 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

W dniu 03.11.2017 o 01:00, Francisco Iglesias pisze: Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice,

Re: [Qemu-devel] [PATCH v6 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

Hi Francisco, W dniu 01.11.2017 o 08:16, Francisco Iglesias pisze: Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST,

Re: [Qemu-devel] [PATCH v5 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

W dniu 31.10.2017 o 12:26, francisco iglesias pisze: Hi Marcin, Huge thank you once again for reviewing and your time! I'll update above i next version of the patch series. I'll remove the Acks so the patch can be revisited (if it is ok for you that keep it just let me know and I'll do

Re: [Qemu-devel] [PATCH v5 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60)

W dniu 29.10.2017 o 11:13, Francisco Iglesias pisze: Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński ---

Re: [Qemu-devel] [PATCH v5 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

Hi Fancisco, W dniu 29.10.2017 o 22:13, francisco iglesias pisze: On 29 October 2017 at 16:21, mar.krzeminski <mar.krzemin...@gmail.com <mailto:mar.krzemin...@gmail.com>> wrote: W dniu 29.10.2017 o 11:13, Francisco Iglesias pisze: Add support for SST READ

Re: [Qemu-devel] [PATCH v5 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

W dniu 29.10.2017 o 11:13, Francisco Iglesias pisze: Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis ---

Re: [Qemu-devel] [PATCH v5 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

W dniu 29.10.2017 o 11:13, Francisco Iglesias pisze: Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice,

Re: [Qemu-devel] [PATCH v3 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands

W dniu 24.10.2017 o 21:51, Francisco Iglesias pisze: Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 20 1 file changed, 20

Re: [Qemu-devel] [PATCH v3 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR

W dniu 24.10.2017 o 21:51, Francisco Iglesias pisze: Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice,

Re: [Qemu-devel] [PATCH v3 04/13] m25p80: Add support for n25q512a11 and n25q512a13

W dniu 24.10.2017 o 21:51, Francisco Iglesias pisze: Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński --- hw/block/m25p80.c | 2 ++ 1 file changed, 2

Re: [Qemu-devel] [PATCH v3 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60)

W dniu 24.10.2017 o 21:51, Francisco Iglesias pisze: Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 20 1 file changed, 20

Re: [Qemu-devel] [PATCH v3] aspeed/smc: handle dummy bytes when doing fast reads in command mode

W dniu 18.01.2017 o 16:01, Cédric Le Goater pisze: When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers to the flash module. This only supports command

Re: [Qemu-devel] [PATCH v2 09/11] aspeed/smc: extend tests for Command mode

W dniu 17.01.2017 o 09:34, Cédric Le Goater pisze: On 01/16/2017 06:51 PM, mar.krzeminski wrote: W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller

Re: [Qemu-devel] [PATCH v2 11/11] aspeed/smc: handle dummy bytes when doing fast reads in command mode

W dniu 17.01.2017 o 09:37, Cédric Le Goater pisze: On 01/16/2017 07:58 PM, mar.krzeminski wrote: W dniu 16.01.2017 o 09:18, Cédric Le Goater pisze: I did not notice that this function is also called in writes, isn't it? If yes, dummy cycles are used only during reads so probably

Re: [Qemu-devel] [PATCH v6] hw/ssi/imx_spi.c: fix CS handling during SPI access.

W dniu 16.01.2017 o 18:22, Peter Maydell pisze: On 11 January 2017 at 20:00, Jean-Christophe Dubois wrote: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI

Re: [Qemu-devel] [PATCH v2 11/11] aspeed/smc: handle dummy bytes when doing fast reads in command mode

W dniu 16.01.2017 o 09:18, Cédric Le Goater pisze: I did not notice that this function is also called in writes, isn't it? If yes, dummy cycles are used only during reads so probably CTRL_FREADMODE needs to be tested. yes. I can take care of that in a follow up patchset for dummy support.

Re: [Qemu-devel] [PATCH v2 08/11] aspeed/smc: reset flash after each test

W dniu 16.01.2017 o 19:10, Cédric Le Goater pisze: On 01/16/2017 06:37 PM, mar.krzeminski wrote: W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: Let's make sure when each test is run that the flash object is in an initial state and did not keep configuration from the previous tests

Re: [Qemu-devel] [PATCH v2 09/11] aspeed/smc: extend tests for Command mode

W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. So add a couple of tests

Re: [Qemu-devel] [PATCH v2 08/11] aspeed/smc: reset flash after each test

W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: Let's make sure when each test is run that the flash object is in an initial state and did not keep configuration from the previous tests. Is there any particukar reason why you do that (bug/side effect/whatever) or you just want to be sure

Re: [Qemu-devel] [PATCH v2 02/11] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function

W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: Instead, we can simply set the irq level when unselecting the slave devices. This change prepares ground for a subsequent cleanup of the aspeed_smc_update_cs() routine which uselessly loops on all slaves to update their status. Signed-off-by:

Re: [Qemu-devel] [PATCH v2 11/11] aspeed/smc: handle dummy bytes when doing fast reads in command mode

W dniu 11.01.2017 o 19:55, Cédric Le Goater pisze: On 01/11/2017 07:20 PM, mar.krzeminski wrote: W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control

Re: [Qemu-devel] [PATCH v2 11/11] aspeed/smc: handle dummy bytes when doing fast reads in command mode

W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers the flash module. Signed-off-by: Cédric Le

Re: [Qemu-devel] [PATCH v2 01/11] aspeed/smc: remove call to reset in realize function

W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze: This is useless as reset will be called later on. Signed-off-by: Cédric Le Goater Acked-by: Marcin Krzemiński --- hw/ssi/aspeed_smc.c | 2 -- 1 file changed, 2 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

W dniu 11.01.2017 o 17:12, Jean-Christophe DUBOIS pisze: Le 10/01/2017 à 00:02, Peter Maydell a écrit : On 9 January 2017 at 22:27, Jean-Christophe DUBOIS wrote: I might be wrong but I think they are coming out of reset with their CS line set to low (so they are selected

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

W dniu 09.01.2017 o 11:46, Peter Maydell pisze: On 4 January 2017 at 22:06, Jean-Christophe Dubois wrote: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI

Re: [Qemu-devel] [PATCH v2 2/3] block: m25p80: Introduce die erase command

W dniu 07.01.2017 o 20:57, Cédric Le Goater pisze: On 01/06/2017 07:49 PM, Marcin Krzeminski wrote: Modern big flash nor devices consist from more than one die. Some of them do not support chip erase and instead have die erase command that can erase one die only. This commit adds possibility

Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

W dniu 06.01.2017 o 19:18, Jean-Christophe DUBOIS pisze: Le 06/01/2017 à 13:28, mar.krzeminski a écrit : Please make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's after reset/power up (defaults). There is already a memset to 0 of all regs (including CONFIGREG) in the reset function

Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

W dniu 04.01.2017 o 22:54, Jean-Christophe DUBOIS pisze: Le 04/01/2017 à 21:56, mar.krzeminski a écrit : W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

Hi Peter, W dniu 05.01.2017 o 19:38, Peter Maydell pisze: On 3 January 2017 at 21:17, Jean-Christophe Dubois wrote: Signed-off-by: Jean-Christophe Dubois --- hw/block/m25p80.c | 19 +-- 1 file changed, 17 insertions(+), 2

Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whit this path the CS signal is correctly asserted and

Re: [Qemu-devel] [PATCH v2] [i.MX] fix CS handling during SPI access.

Hello JC, W dniu 02.01.2017 o 22:11, Jean-Christophe Dubois pisze: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whit this path the CS signal is correctly asserted

Re: [Qemu-devel] [PATCH] [M25P80] Make sure not to overrun the internal data buffer.

W dniu 02.01.2017 o 22:24, Jean-Christophe DUBOIS pisze: Le 30/12/2016 à 19:09, mar.krzeminski a écrit : Can you check spi controller model code? I'll double check. But why is the SPI memory/device even responding if CS is not set ? Looking at ssi code it should not. Flash (so the m25p80

Re: [Qemu-devel] [PATCH for-2.9 17/30] aspeed/smc: handle SPI flash Command mode

W dniu 02.01.2017 o 19:02, Cédric Le Goater pisze: On 01/02/2017 06:33 PM, mar.krzeminski wrote: Hello Cedric, W dniu 02.01.2017 o 16:56, Cédric Le Goater pisze: Hello Marcin, On 12/05/2016 04:33 PM, mar.krzeminski wrote: W dniu 05.12.2016 o 15:07, Cédric Le Goater pisze: On 12/04/2016

Re: [Qemu-devel] [PATCH for-2.9 17/30] aspeed/smc: handle SPI flash Command mode

Hello Cedric, W dniu 02.01.2017 o 16:56, Cédric Le Goater pisze: Hello Marcin, On 12/05/2016 04:33 PM, mar.krzeminski wrote: W dniu 05.12.2016 o 15:07, Cédric Le Goater pisze: On 12/04/2016 05:31 PM, mar.krzeminski wrote: Hi Cedric, Since there is no public datasheet user guide for SMC I

Re: [Qemu-devel] [PATCH] [M25P80] Make sure not to overrun the internal data buffer.

W dniu 30.12.2016 o 18:14, Jean-Christophe DUBOIS pisze: Le 30/12/2016 à 16:39, mar.krzeminski a écrit : I got some time, and reproduced the problem. Here are some logs with m25p80 debugs: : decode_new_cmd: decoded new command:9f : decode_new_cmd: populated jedec code : decode_new_cmd

Re: [Qemu-devel] [PATCH] [M25P80] Make sure not to overrun the internal data buffer.

to start the guest to see the crash. Just boot Xvisor ... JC Le 24/12/2016 à 19:12, Jean-Christophe DUBOIS a écrit : Le 24/12/2016 à 19:04, mar.krzeminski a écrit : W dniu 24.12.2016 o 18:41, Jean-Christophe DUBOIS pisze: Le 24/12/2016 à 18:18, mar.krzeminski a écrit : Hello, W dniu 24.12.2016 o

Re: [Qemu-devel] [PATCH] [M25P80] Make sure not to overrun the internal data buffer.

W dniu 24.12.2016 o 18:41, Jean-Christophe DUBOIS pisze: Le 24/12/2016 à 18:18, mar.krzeminski a écrit : Hello, W dniu 24.12.2016 o 16:11, Jean-Christophe Dubois pisze: It did happen that the internal data buffer was overrun leading to a Qemu crash (in particular while emulating the i.MX6

Re: [Qemu-devel] [PATCH] [M25P80] Make sure not to overrun the internal data buffer.

Hello, W dniu 24.12.2016 o 16:11, Jean-Christophe Dubois pisze: It did happen that the internal data buffer was overrun leading to a Qemu crash (in particular while emulating the i.MX6 sabrelite board). This patch makes sure the data array would not be overrun and allow the sabrelite emulation

Re: [Qemu-devel] [PATCH for-2.9 17/30] aspeed/smc: handle SPI flash Command mode

W dniu 05.12.2016 o 15:07, Cédric Le Goater pisze: On 12/04/2016 05:31 PM, mar.krzeminski wrote: Hi Cedric, Since there is no public datasheet user guide for SMC I would ask some question regarding HW itself because I got impression that you are implementing in this model a part

Re: [Qemu-devel] [PATCH for-2.9 22/30] aspeed/smc: handle dummy bytes when doing fast reads

W dniu 05.12.2016 o 15:14, Cédric Le Goater pisze: On 12/04/2016 05:46 PM, mar.krzeminski wrote: W dniu 29.11.2016 o 16:44, Cédric Le Goater pisze: When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control

Re: [Qemu-devel] [PATCH for-2.9 24/30] aspeed: use first SPI flash as a boot ROM

W dniu 05.12.2016 o 15:53, Cédric Le Goater pisze: On 12/05/2016 10:57 AM, Marcin Krzemiński wrote: 2016-12-05 10:36 GMT+01:00 Cédric Le Goater <c...@kaod.org <mailto:c...@kaod.org>>: Hello Marcin, On 12/04/2016 06:00 PM, mar.krzeminski wrote:

Re: [Qemu-devel] [PATCH for-2.9 24/30] aspeed: use first SPI flash as a boot ROM

Hi Cedric, it looks like good idea for now to handle boot from flash. As I understand you are trying to omit bootrom code in Qemu model? This could lead you to some hacks in device models (eg SMC). W dniu 29.11.2016 o 16:44, Cédric Le Goater pisze: Fill a ROM region with the flash content to

Re: [Qemu-devel] [PATCH for-2.9 22/30] aspeed/smc: handle dummy bytes when doing fast reads

W dniu 29.11.2016 o 16:44, Cédric Le Goater pisze: When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers the flash module. When the controller is

Re: [Qemu-devel] [PATCH for-2.9 17/30] aspeed/smc: handle SPI flash Command mode

Hi Cedric, Since there is no public datasheet user guide for SMC I would ask some question regarding HW itself because I got impression that you are implementing in this model a part functionality that is done by Bootrom. W dniu 29.11.2016 o 16:43, Cédric Le Goater pisze: The Aspeed SMC

Re: [Qemu-devel] 9p as rootfs

=none,path=work/rootfs/ / Thanks, Marcin/ / W dniu 23.09.2016 o 21:41, mar.krzeminski pisze: And most important, while mounting as roots, error is: [1.086235] device: '9p-1': device_add [1.087859] 9pnet_virtio: no channels available [1.091619] device: '9p-1': device_unregister

Re: [Qemu-devel] [Qemu-arm] [PATCH 4/7] m25p80: add a m25p80_set_rom_storage() routine

W dniu 26.09.2016 o 10:56, Cédric Le Goater pisze: On 09/26/2016 10:25 AM, KONRAD Frederic wrote: Le 24/09/2016 à 10:55, Edgar E. Iglesias a écrit : On Sat, Sep 24, 2016 at 10:25:39AM +0200, Cédric Le Goater wrote: On 09/23/2016 08:26 PM, mar.krzeminski wrote: Hi Cedric, W dniu

Re: [Qemu-devel] 9p as rootfs

"host" or unknown-block(0,0): error -2 Thanks, Marcin W dniu 23.09.2016 o 21:38, mar.krzeminski pisze: Hello, I have a problem in my custom arm machine to use 9p fs as a rootfs. 9p command line i qemu: /-device virtio-9p-device,fsdev=host_fs,mount_tag=hostfs -fsdev local,

[Qemu-devel] 9p as rootfs

Hello, I have a problem in my custom arm machine to use 9p fs as a rootfs. 9p command line i qemu: /-device virtio-9p-device,fsdev=host_fs,mount_tag=hostfs -fsdev local,id=host_fs,security_model=none,path=/work/rootfs/ Kernel cmd line: /--append "root=hostfs rootfstype=9p

Re: [Qemu-devel] [PATCH 4/7] m25p80: add a m25p80_set_rom_storage() routine

Hi Cedric, W dniu 23.09.2016 o 10:28, Cédric Le Goater pisze: On 09/23/2016 10:17 AM, Peter Maydell wrote: On 23 September 2016 at 08:19, Cédric Le Goater wrote: But the goal is to boot from the device, so I added a memory region alias at 0 to trigger the flash module mmios at

Re: [Qemu-devel] hw/arm/virt: vmstate-static-checker.py results

W dniu 18.08.2016 o 21:05, Peter Maydell pisze: On 18 August 2016 at 20:04, Dr. David Alan Gilbert wrote: Hmm, except there are two separate things with the name "xilinx_spi"; vmstate_xilinx_spi in hw/ssi/xilinx_spi.c which is the state for the "xlnx.xps-spi" (aka

Re: [Qemu-devel] [PATCH 4/7] m25p80: add a m25p80_set_rom_storage() routine

W dniu 06.07.2016 o 18:30, Cédric Le Goater pisze: On 07/04/2016 08:12 PM, Cédric Le Goater wrote: On 07/04/2016 07:57 PM, mar.krzeminski wrote: W dniu 04.07.2016 o 14:18, Cédric Le Goater pisze: Some SPI controllers, such as the Aspeed AST2400, have a mode in which accesses to the flash

Re: [Qemu-devel] [PATCH 4/7] m25p80: add a m25p80_set_rom_storage() routine

W dniu 04.07.2016 o 20:12, Cédric Le Goater pisze: On 07/04/2016 07:57 PM, mar.krzeminski wrote: W dniu 04.07.2016 o 14:18, Cédric Le Goater pisze: Some SPI controllers, such as the Aspeed AST2400, have a mode in which accesses to the flash content are no different than doing MMIOs

Re: [Qemu-devel] [PATCH 4/7] m25p80: add a m25p80_set_rom_storage() routine

W dniu 04.07.2016 o 14:18, Cédric Le Goater pisze: Some SPI controllers, such as the Aspeed AST2400, have a mode in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. To emulate such a

Re: [Qemu-devel] [PATCH v5 9/9] tests: add a m25p80 test

W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: This test uses the palmetto platform and the AST2400 SPI controller to test the m25p80 flash module device model. The flash model is defined by the platform (n25q256a) and it would be nice to find way to control it, using a property probably.

Re: [Qemu-devel] [PATCH v5 7/9] ast2400: add SPI flash slaves

W dniu 02.07.2016 o 19:08, mar.krzeminski pisze: W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: Each controller on the ast2400 has a memory range on which it maps its flash module slaves. Each slave is assigned a memory segment for its mapping that can be changed at bootime

Re: [Qemu-devel] [PATCH v5 7/9] ast2400: add SPI flash slaves

W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: Each controller on the ast2400 has a memory range on which it maps its flash module slaves. Each slave is assigned a memory segment for its mapping that can be changed at bootime with the Segment Address Register. This is not supported in the

Re: [Qemu-devel] [PATCH v5 6/9] ast2400: add SMC controllers (FMC and SPI)

W dniu 29.06.2016 o 09:58, Cédric Le Goater pisze: On 06/28/2016 08:24 PM, Cédric Le Goater wrote: The Aspeed AST2400 soc includes a static memory controller for the BMC which supports NOR, NAND and SPI flash memory modules. This controller has two modes : the SMC for the legacy interface

Re: [Qemu-devel] qemu -nographics option

Hello, Have you try to add chardev device? -chardev stdio,mux=on,id=terminal -serial chardev:terminal I am also not sure if you so many consoles in kernel command line, since you do not want to use any graphic mode. Regards, Marcin W dniu 11.06.2016 o 16:22, David Craven pisze: Hello qemu

Re: [Qemu-devel] [PATCH 2/3] i.MX: Add the Freescale SPI Controller

W dniu 15.02.2016 o 23:43, Jean-Christophe DUBOIS pisze: Le 15/02/2016 17:46, mar.krzeminski a écrit : W dniu 15.02.2016 o 11:18, Jean-Christophe DUBOIS pisze: Le 14/02/2016 20:17, mar.krzeminski a écrit : W dniu 14.02.2016 o 17:56, Jean-Christophe DUBOIS pisze: Le 14/02/2016 12:52

Re: [Qemu-devel] [PATCH 2/3] i.MX: Add the Freescale SPI Controller

W dniu 15.02.2016 o 11:18, Jean-Christophe DUBOIS pisze: Le 14/02/2016 20:17, mar.krzeminski a écrit : W dniu 14.02.2016 o 17:56, Jean-Christophe DUBOIS pisze: Le 14/02/2016 12:52, mar.krzeminski a écrit : Hello, W dniu 13.02.2016 o 17:06, Jean-Christophe Dubois pisze: Signed-off

Re: [Qemu-devel] [PATCH 2/3] i.MX: Add the Freescale SPI Controller

W dniu 14.02.2016 o 17:56, Jean-Christophe DUBOIS pisze: Le 14/02/2016 12:52, mar.krzeminski a écrit : Hello, W dniu 13.02.2016 o 17:06, Jean-Christophe Dubois pisze: Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net> --- hw/ssi/Makefile.objs | 1 + hw/ssi/imx

Re: [Qemu-devel] [PATCH 2/3] i.MX: Add the Freescale SPI Controller

Hello, W dniu 13.02.2016 o 17:06, Jean-Christophe Dubois pisze: Signed-off-by: Jean-Christophe Dubois --- hw/ssi/Makefile.objs | 1 + hw/ssi/imx_spi.c | 449 +++ include/hw/ssi/imx_spi.h | 104 +++ 3

Re: [Qemu-devel] [RFC PATCH 0/8] Towards an Heterogeneous QEMU

W dniu 25.10.2015 o 22:38, Peter Crosthwaite pisze: On Thu, Oct 22, 2015 at 2:21 AM, Christian Pinto wrote: Hello Peter, On 07/10/2015 17:48, Peter Crosthwaite wrote: On Mon, Oct 5, 2015 at 8:50 AM, Christian Pinto wrote:

Re: [Qemu-devel] Arm virtual machine networking problem with build for 64bit host

Hello, Problem solved, there was bug in my gmac model, that cause writes outside my gmac device state structure. That leads to such (undefined) behaviour. Regards, Marcin W dniu 10.10.2015 o 22:34, mar.krzeminski pisze: Hello, I have my own virtual machine (already asked some questions

[Qemu-devel] Arm virtual machine networking problem with build for 64bit host

Hello, I have my own virtual machine (already asked some questions about that here). I also have my own gmac model. I am building qemu (version 2.4.0.1) for 32 and 64 linux hosts. The problem is with 64 bit binary. If I run as guest under qemu linux, I could not even ping my machine. In 32

[Qemu-devel] Debugging u-boot after relocation on arm machie

Hello, I am working on u-boot under qemu. Debugging before u-boots relocate itself works just fine. After relocation and reloading elf in gdb, qemu does no stop on breakpoint. Generally I follow this instruction: http://www.denx.de/wiki/view/DULG/DebuggingUBoot I am debuging under eclipse -

Re: [Qemu-devel] Starting A9 from M3

The problem was related to my SDRAM hw specific implementation. There is only 64KiB starting from address 0xFFF0, but the address space has 1MiB. Space above 64KiB is constantly remapped to real location. In my model I used 1MiB memory chunk instead of aliasing, so the A9s reset vector has

Re: [Qemu-devel] Triggering two arm processors from same interrupt (A9 and M3)

W dniu 26.09.2015 o 19:46, Peter Crosthwaite pisze: On Sat, Sep 26, 2015 at 9:08 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: On 26 September 2015 at 01:54, mar.krzeminski <mar.krzemin...@gmail.com> wrote: Hello again, My next question is still related with M3 and A9

[Qemu-devel] Triggering two arm processors from same interrupt (A9 and M3)

Hello again, My next question is still related with M3 and A9 board what I want to model. This time my peripheral has some interrupts that are connected both to A9 processor(gic), and M3 processor (nvic). Additionally those interrupts have same number. Currently I use only two in my model so I

Re: [Qemu-devel] Loading image/elf to cpu that has different not system memory address space

W dniu 24.09.2015 o 20:38, Peter Crosthwaite pisze: On Thu, Sep 24, 2015 at 10:14 AM, mar.krzeminski <mar.krzemin...@gmail.com> wrote: W dniu 24.09.2015 o 05:07, Peter Crosthwaite pisze: On Wed, Sep 23, 2015 at 8:06 PM, Peter Crosthwaite <crosthwaitepe...@gmail.com> wrote: On

Re: [Qemu-devel] Loading image/elf to cpu that has different not system memory address space

W dniu 24.09.2015 o 05:07, Peter Crosthwaite pisze: On Wed, Sep 23, 2015 at 8:06 PM, Peter Crosthwaite <crosthwaitepe...@gmail.com> wrote: On Wed, Sep 23, 2015 at 10:31 AM, mar.krzeminski <mar.krzemin...@gmail.com> wrote: W dniu 23.09.2015 o 17:46, Peter Maydell pisze: On 23 Se

Re: [Qemu-devel] Loading image/elf to cpu that has different not system memory address space

W dniu 23.09.2015 o 17:46, Peter Maydell pisze: On 23 September 2015 at 08:17, Marcin Krzemiński wrote: Hello, I am trying to write a model of embedded board that have corterx-m3 and cotex a9 processors. Because M3 see different memory at address 0x0 than A9 (m3 has

[Qemu-devel] Adding secondary ARM processor

Hello, I have board with A9 processor (playing with vexpress model), for test I want to also add to this setup M3 processor. The problem is that secondary CPU sees the same device (eg. UART) with different address. I can not figure out, how should I do that. Is it possible in qemu? If yes,

Re: [Qemu-devel] Adding secondary ARM processor

W dniu 01.09.2015 o 19:45, Peter Crosthwaite pisze: On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski <mar.krzemin...@gmail.com> wrote: Hello, I have board with A9 processor (playing with vexpress model), for test I want to also add to this setup M3 processor. The problem is that seconda

[Qemu-devel] Reset register configuration in embedde device

Hello, I am new here, so sorry for dummy question... The problem: I have an embedded arm board simulation, I want to add a device simulating quite complicated reset cause logic. This logic is used in boot process. The goal is to have possibility to set proper register values before virtual