[PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 12 hw/i386/intel_iommu_internal.h | 17 + 2 files changed, 21 insertions(+)

[PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones

From: "Zhang, Qi" Signed-off-by: Zhang, Qi --- hw/i386/intel_iommu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8fdb75..a118efaeaf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/

[PATCH v2 0/2] TM field check failed

From: "Zhang, Qi" spilt the reserved fields arrays and remove TM field from reserved bits Changelog V1: add descriptons Changelog V2: refine Zhang, Qi (2): intel_iommu: split the resevred fields arrays into two ones intel_iommu: TM field should not be in reserved bits hw/i386/intel_io

[PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones

From: "Zhang, Qi" Signed-off-by: Zhang, Qi --- hw/i386/intel_iommu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8fdb75..a118efaeaf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/

[PATCH 2/2] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 12 hw/i386/intel_iommu_internal.h | 17 + 2 files changed, 21 insertions(+)

[PATCH 0/2] TM field check failed

From: "Zhang, Qi" *** BLURB HERE *** Zhang, Qi (2): intel_iommu: split the resevred fields arrays into two ones intel_iommu: TM field should not be in reserved bits hw/i386/intel_iommu.c | 35 -- hw/i386/intel_iommu_internal.h | 17 +

[PATCH v4] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 12 hw/i386/intel_iommu_internal.h | 17 + 2 files changed, 21 insertions(+)

[PATCH v3] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 8 hw/i386/intel_iommu_internal.h | 17 + 2 files changed, 17 insertions(+), 8

[PATCH] intel_iommu: split the resevred fields arrays into two ones

From: "Zhang, Qi" Signed-off-by: Zhang, Qi --- hw/i386/intel_iommu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8fdb75..a118efaeaf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/

[PATCH V2] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 12 ++-- hw/i386/intel_iommu_internal.h | 25 +++-- 2 files changed, 25 inser

[PATCH] intel_iommu: TM field should not be in reserved bits

From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8