Update mail account

Hi, all. I'v left my job at Iscas. The old iscas mail acount will be disabled soon. So I'll change to use my personal gmail acount (liwei1...@gmail.com) for future reviewer tasks. Regards, Weiwei Li Weiwei Li (1): MAINTAINERS: update mail address for Weiwei Li MAINTAINERS | 2

[PATCH 1/1] MAINTAINERS: update mail address for Weiwei Li

My Iscas mail account will be disabled soon, change to my personal gmail account. Signed-off-by: Weiwei Li --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cd8d6b140f..aa5c5d4bff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS

[PATCH v2] target/riscv: Update CSR bits name for svadu extension

The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- v2: * rename hade variable name to adue suggested by Daniel target/riscv/cpu.c| 4 ++-- target/riscv/cpu_bits.h | 8 target/riscv

[PATCH] target/riscv: Update CSR bits name for svadu extension

The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 4 ++-- target/riscv/cpu_bits.h | 8 target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c| 12

Re: [PATCH v6 09/12] target/riscv/cpu.c: limit cfg->vext_spec log message

it's strange to force users to set 'vext_spec' to get rid of this message. Change riscv_cpu_validate_v() to not throw this log message if env->vext_ver is already set. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c |

Re: [PATCH] target/riscv: Fix zfa fleq.d and fltq.d

On 2023/7/28 08:39, LIU Zhiwei wrote: Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s helper function. Signed-off-by: LIU Zhiwei --- Reviewed-by:

Re: [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string

On 2023/7/20 21:24, Daniel Henrique Barboza wrote: The cpu->cfg.epmp extension is still experimental, but it already has a 'smepmp' riscv,isa string. Add it. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 1 + 1 fi

Re: [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string

ue Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..d64ac07558 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,6 +88,7 @@ static const struct isa_ext_data isa

Re: [PATCH for-8.2 v5 08/11] target/riscv/cpu.c: add ADD_UNAVAIL_KVM_PROP_ARRAY() macro

On 2023/7/21 01:19, Daniel Henrique Barboza wrote: Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition, similar to what we're already doing with ADD_CPU_QDEV_PROPERTIES_ARRAY(). Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiw

Re: [PATCH for-8.2 v5 04/11] target/riscv/cpu.c: del DEFINE_PROP_END_OF_LIST() from riscv_cpu_extensions

to encapsulate more repetitions in macros later on. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f0852a14e..4d

Re: [PATCH for-8.2 v5 03/11] target/riscv/cpu.c: split kvm prop handling to its own helper

dd. The rest of riscv_cpu_add_user_properties() body will then be relieved from having to deal with KVM constraints. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 65 ++ 1 file changed, 42 insertions(+), 23 deletions(-

Re: [PATCH for-8.2 v5 01/11] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --gi

Re: [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support

_0}, +[CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf, read_minstretcfgh, + write_minstretcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0}, This two CSRs are RV32-only, they cannot directly share the same predicate as MCYCLECFG

Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties

fpmf", RISCVCPU, cfg.ext_sscofpmf, false), +DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), Normally, property should be exposed to user at last after the function is implemented. Regards, Weiwei Li DEFINE_PROP_BOOL("Zifence

Re: [PATCH v2] target/riscv: Fix LMUL check to use VLEN

: configure instructions") Signed-off-by: Rob Bradford --- V2: Switch check to use VLEN and active SEW vs ELEN and minimum SEW --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/v

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

On 2023/7/17 23:13, Rob Bradford wrote: On Thu, 2023-07-06 at 21:22 +0800, Weiwei Li wrote: On 2023/7/6 18:44, Rob Bradford wrote: The previous check was failing with: ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid combination. Fix the check to correctly match the

Re: [PATCH] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

("target/riscv: add cfg properties for Zc* extension") Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..6b93

Re: [PATCH for-8.2 v3 6/8] target/riscv: add 'max' CPU type

disabled. This is the resulting 'riscv,isa' DT for this new CPU: rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_ zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_ zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_ smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt Signed-off-by: Daniel Henrique Barboza --- R

Re: [PATCH for-8.2 v3 5/8] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro

On 2023/7/15 01:43, Daniel Henrique Barboza wrote: The code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a macro to hide the repetition away. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

pec in another way: we must support lmul=1/8 when ELEN=64, but it's only available when sew = 8. Regards, Weiwei Li ` Regards, Weiwei Li Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford --- target/riscv/vector_helper.c |

[PATCH v3 1/1] target/riscv: Add disas support for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 44 1 file changed, 44 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 94e568a7e9..9f0195be30 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -819,6 +819,16

[PATCH v3 0/1] target/riscv: Add support for BF16 extensions

extensions in patch 1 and patch 4 * Update encodings for BF16 instructions in patch 2,3,4 * Add disas support for BF16 instructions in patch 6 Weiwei Li (1): target/riscv: Add disas support for BF16 extensions disas/riscv.c | 44 1 file changed, 44

Re: [PATCH 2/2] target/riscv: Optimize ambiguous local variable in pmp_hart_has_privs

a_field)) { +if ((sa_in & ea_in) && (PMP_AMATCH_OFF != a_field)) { I think it's better to use "sa_in && ea_in &&(...)" here. Regards, Weiwei Li /* * If the PMP entry is not off and the address is in range, * do the priv check

Re: [PATCH 1/2] target/riscv: Remove redundant check in pmp_is_locked

On 2023/6/28 18:36, Ruibo Lu wrote: the check of top PMP is redundant and will not influence the return value, so consider remove it Signed-off-by: Ruibo Lu --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/pmp.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv

Re: [PATCH] hw/riscv/virt.c: fix typo in 'aia' description

On 2023/6/15 17:21, Daniel Henrique Barboza wrote: Cc: qemu-triv...@nongnu.org Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

On 2023/6/15 20:58, Rob Bradford wrote: On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote: Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. Add require check for BF16 extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza ---  target/riscv

Re: [PATCH v2 8/8] disas/riscv: Add support for XThead* instructions

mm = operand_imm6(inst); +break; +case rv_codec_r_imm2: +dec->rd = operand_rd(inst); +dec->rs1 = operand_rs1(inst); +dec->rs2 = operand_rs2(inst); +dec->imm = operand_imm2(inst); +break; +case rv_codec_r2_immhl: +dec->rd = operand_

Re: [PATCH v2 2/8] target/riscv: Factor out extension tests to cpu_cfg.h

patch includes a small change: The parameter for the extension test functions has been changed from 'DisasContext*' to 'const RISCVCPUConfig*' to keep the code in cpu_cfg.h self-contained. Signed-off-by: Christoph Müllner --- Reviewed-by: Weiwei Li Weiwei Li target/ri

[PATCH v2 3/6] target/riscv: Add support for Zvfbfmin extension

Add trans_* and helper function for Zvfbfmin instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvbf16.c.inc

[PATCH v2 2/6] target/riscv: Add support for Zfbfmin extension

Add trans_* and helper function for Zfbfmin instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode

[PATCH v2 6/6] target/riscv: Add disas support for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 44 1 file changed, 44 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 5005364aba..44ea69315c 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -964,6 +964,16

[PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension

Add trans_* and helper function for Zvfbfwma instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvbf16

[PATCH v2 0/6] target/riscv: Add support for BF16 extensions

in patch 2,3,4 * Add disas support for BF16 instructions in patch 6 Weiwei Li (6): target/riscv: Add properties for BF16 extensions target/riscv: Add support for Zfbfmin extension target/riscv: Add support for Zvfbfmin extension target/riscv: Add support for Zvfbfwma extension target

[PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. Add require check for BF16 extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 20 target/riscv/cpu_cfg.h | 3 +++ 2 files changed, 23 insertions

[PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dc6b2f72f6..feb0ee5e6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv

[PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1

Currently, we use the current env->xl as the xlen for address. However, the xlen for data address should be changed to the xlen related to MPP when MPRV=1. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream Weiwei Li (2): target/riscv: Add additio

[PATCH 1/2] target/riscv: Add additional xlen for address when MPRV=1

As specified in privilege spec:"When MPRV=1, load and store memory addresses are treated as though the current XLEN were set to MPP’s XLEN". So the xlen for address may be different from current xlen. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h

[PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV

Pointer mask is also affected by MPRV which means cur_pmbase/pmmask should also take MPRV into consideration. As pointer mask for instruction is not supported currently, so we can directly update cur_pmbase/pmmask based on address related mode and xlen affected by MPRV now. Signed-off-by: Weiwei

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 13:40, LIU Zhiwei wrote: On 2023/6/12 12:35, Weiwei Li wrote: On 2023/6/12 11:18, LIU Zhiwei wrote: On 2023/6/12 11:16, Weiwei Li wrote: On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 11:18, LIU Zhiwei wrote: On 2023/6/12 11:16, Weiwei Li wrote: On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Have you found the CSR field specifications

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Have you found the CSR field specifications for them, especially for GVA. Yeah.  in the section 9.4.1 of the privilege spec

Re: [PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M

On 2023/6/12 10:45, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: Upon MRET or explicit memory access with MPRV=1, MPV should be ignored when MPP=PRV_M. Does MPP==PRV_M always indicate the MPV==0? No, I think . The spec doesn't restrict this. When MPP=PRV_M, MPV wll be

[PATCH] target/riscv: Fix initialized value for cur_pmmask

. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 09ea227ceb..acbcb7ed76 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

Re: [PATCH v2] target/riscv/vector_helper.c: Remove the check for extra tail elements

("target/riscv: rvv: Add tail agnostic for vector load / store instructions") Signed-off-by: Xiao Wang --- Reviewed-by: Weiwei Li Weiwei Li v2: * Rebased on top of Alistair's riscv-to-apply.next branch. --- target/riscv/vector_helper.c | 22 ++ 1 fil

Re: [PATCH v3] target/riscv: Smepmp: Return error when access permission not allowed in PMP

return in place when address matches o Call pmp_hart_has_privs_default at the end of the loop Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when address matches") Signed-off-by: Himanshu Chauhan --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/

Re: [PATCH v2] target/riscv: Smepmp: Return error when access permission not allowed in PMP

break; +return (privs & *allowed_privs) == privs ? true : false; This conditional assignment is unnecessary. +  return  (privs & *allowed_privs) == privs; Otherwise, Reviewed-by: Weiwei Li Weiwei Li } }

Re: [PATCH] target/riscv: Smepmp: Return error when access permission not allowed in PMP

to _address_matched; goto seems unnecessary. We can directly return (privs & *allowed_privs) == privs here. And then we can directly return pmp_hart_has_privs_default(env, privs, allowed_privs, mode) after this loop. Regards, Weiwei Li } } @@ -445,6 +445,7 @@

Re: [PATCH 2/4] target/riscv: Remove check on mode for MPRV

On 2023/6/3 05:01, Richard Henderson wrote: On 6/1/23 18:31, Weiwei Li wrote: Even though MPRV normally can be set to 1 in M mode, it seems possible to set it to 1 in other mode by gdbstub. That would seem to be a gdbstub bug, since it is cleared on exit from M-mode, and cannot be set

[PATCH v2 3/3] target/riscv: Remove redundant assignment to SXL

SXL is initialized as env->misa_mxl which is also the mxl value. So we can just remain it unchanged to keep it read-only. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/csr.c | 4 1 file chan

[PATCH v2 0/3] target/riscv: Fix mstatus related problems

This patchset tries to fix some problems in the fields of mstatus, such as make MPV only work when MPP != PRM. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream-v2 v2: * Drop patch 3 (remove check on mode M for MPRV) * rebase on apply-to-riscv.next Weiwei

[PATCH v2 1/3] target/riscv: Make MPV only work when MPP != PRV_M

Upon MRET or explicit memory access with MPRV=1, MPV should be ignored when MPP=PRV_M. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 ++- target/riscv/op_helper.c | 3 ++- 2 files

[PATCH v2 2/3] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/csr.c | 10 -- 1 file changed, 4 insertions(+), 6

Re: [PATCH 1/2] target/riscv: Add Zacas ISA extension support

clude "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzicond.c.inc" +#include "insn_trans/trans_rvzacas.c.inc" #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzfh.c.inc" It seems lack check on "Zacas requires A" Regards, Weiwei Li

Re: [PATCH 1/2] target/riscv: Add Zacas ISA extension support

On 2023/6/2 20:16, Rob Bradford wrote: This commit adds support for the the amocas.{w,d,q} instructions behind a new property to enable that instruction. Signed-off-by: Rob Bradford --- I also implemented an initial version for this extension without any tests a few days ago. You can fin

Re: [PATCH 2/4] target/riscv: Remove check on mode for MPRV

On 2023/6/2 07:03, Alistair Francis wrote: On Thu, Jun 1, 2023 at 4:43 PM Weiwei Li wrote: On 2023/6/1 13:27, Alistair Francis wrote: On Mon, May 29, 2023 at 10:19 PM Weiwei Li wrote: Normally, MPRV can be set to 1 only in M mode (It will be cleared when returning to lower-privilege mode

Re: [PATCH 2/4] target/riscv: Remove check on mode for MPRV

On 2023/6/1 13:27, Alistair Francis wrote: On Mon, May 29, 2023 at 10:19 PM Weiwei Li wrote: Normally, MPRV can be set to 1 only in M mode (It will be cleared when returning to lower-privilege mode by MRET/SRET). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv

Re: [PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M

On 2023/5/31 04:23, Daniel Henrique Barboza wrote: On 5/29/23 09:17, Weiwei Li wrote: Upon MRET or explicit memory access with MPRV=1, MPV should be ignored when MPP=PRV_M. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   target/riscv/cpu_helper.c | 3 ++-   target/riscv

[PATCH 2/4] target/riscv: Remove check on mode for MPRV

Normally, MPRV can be set to 1 only in M mode (It will be cleared when returning to lower-privilege mode by MRET/SRET). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv

[PATCH 4/4] target/riscv: Remove redundant assignment to SXL

SXL is initialized as env->misa_mxl which is also the mxl value. So we can just remain it unchanged to keep it read-only. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 4 1 file changed, 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/cs

[PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M

Upon MRET or explicit memory access with MPRV=1, MPV should be ignored when MPP=PRV_M. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 3 ++- target/riscv/op_helper.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH 0/4] target/riscv: Fix mstatus related problems

This patchset tries to fix some problems in the fields of mstatus, such as make MPV only work when MPP != PRM. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream Weiwei Li (4): target/riscv: Make MPV only work when MPP != PRV_M target/riscv: Remove check

[PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index

[PATCH v3 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

Reduce reliance on absolute values(by passing pc difference) to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv

[PATCH v3 0/7] target/riscv: Add support for PC-relative translation

or Zc* instructions Weiwei Li (7): target/riscv: Fix target address to update badaddr target/riscv: Introduce cur_insn_len into DisasContext target/riscv: Change gen_goto_tb to work on displacements target/riscv: Change gen_set_pc_imm to gen_update_pc target/riscv: Use true diff for gen_pc_plus

[PATCH v3 2/7] target/riscv: Introduce cur_insn_len into DisasContext

Use cur_insn_len to store the length of the current instruction to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1

[PATCH v3 6/7] target/riscv: Enable PC-relative translation

Add a base pc_save for PC-relative translation(CF_PCREL). Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb. Use gen_pc_plus_diff to get the pc-relative address. Enable CF_PCREL in System mode. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard

[PATCH v3 5/7] target/riscv: Use true diff for gen_pc_plus_diff

Reduce reliance on absolute values by using true pc difference for gen_pc_plus_diff() to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 6

[PATCH v3 3/7] target/riscv: Change gen_goto_tb to work on displacements

Reduce reliance on absolute value to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8

[PATCH v3 1/7] target/riscv: Fix target address to update badaddr

current pc if exception is triggered. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 23 --- target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++-- target/riscv

[PATCH v3 7/7] target/riscv: Remove pc_succ_insn from DisasContext

pc_succ_insn is no longer useful after the introduce of cur_insn_len and all pc related value use diff value instead of absolute value. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 7

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

On 2023/5/24 13:35, Tommy Wu wrote: Hi WeiWei Li, When the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml` for the first time with the correct `base_reg` value. code flow : riscv_cpu_realize → riscv_cpu_register_gdb_regs_for_features  → riscv_gen_dynamic_csr_xml The

Re: [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu.

On 2023/5/24 09:51, Tommy Wu wrote: Hi Weiwei Li, Yes, you're right,  `riscv_refresh_dynamic_csr_xml()`  can only be called when cpu->dyn_csr_xml isn't a NULL pointer here. The cpu->dyn_csr_xml will be set when the cpu is realized. Yeah, It will  be set only when Zicsr is

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

On 2023/5/24 09:59, Tommy Wu wrote: Hi Weiwei Li, `dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml` We can initialize this variable when the cpu is realized. I didn't find this initialization in following code. And used this variable in `riscv_refresh_dynamic_cs

[PATCH v7 2/2] target/riscv: Update cur_pmmask/base when xl changes

write_mstatus() can only change current xl when in debug mode. And we need update cur_pmmask/base in this case. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei --- target/riscv/csr.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a

[PATCH v7 1/2] target/riscv: Fix pointer mask transformation for vector address

actual_address = (requested_address & ~mpmmask) | mpmbase. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/r

[PATCH v7 0/2] target/riscv: Fix pointer mask related support

(patch 3~6) out of this patchset Weiwei Li (2): target/riscv: Fix pointer mask transformation for vector address target/riscv: Update cur_pmmask/base when xl changes target/riscv/csr.c | 9 - target/riscv/vector_helper.c | 2 +- 2 files changed, 9 insertions(+), 2 deletions

Re: [PATCH 2/2] hw/intc: riscv_imsic: Refresh the CSRs xml after updating the state of the cpu.

cpu); + There is an assert in riscv_refresh_dynamic_csr_xml(): +if (!cpu->dyn_csr_xml) { +g_assert_not_reached(); +} So I think riscv_refresh_dynamic_csr_xml() can only be called when cpu->dyn_csr_xml is true here. Regards, Weiwei Li riscv_cpu_set_aia_ireg_rmw_fn(en

Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

riscv_refresh_dynamic_csr_xml(). Regards, Weiwei Li char *dyn_csr_xml; char *dyn_vreg_xml; @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features

[PATCH v2 0/7] target/riscv: Add support for PC-relative translation

And support of PC-relative translation is the precondition to support pointer mask for instruction. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-pcrel-upstream-v2 v2: * rebase on upstream and add pc-relative translation for Zc* instructions Weiwei Li (7): target/

[PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext

Use cur_insn_len to store the length of the current instruction to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target

[PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements

Reduce reliance on absolute value to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 +--- 2 files changed, 7 insertions(+), 5 deletions(-) diff

[PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

Reduce reliance on absolute values(by passing pc difference) to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvi.c.inc| 6 +++--- target/riscv

[PATCH v2 6/7] target/riscv: Enable PC-relative translation

Add a base pc_save for PC-relative translation(CF_PCREL). Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb. Use gen_pc_plus_diff to get the pc-relative address. Enable CF_PCREL in System mode. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c

[PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext

pc_succ_insn is no longer useful after the introduce of cur_insn_len and all pc related value use diff value instead of absolute value. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/translate.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a

[PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff

Reduce reliance on absolute values by using true pc difference for gen_pc_plus_diff() to prepare for PC-relative translation. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvi.c.inc | 6 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 2

[PATCH v2 1/7] target/riscv: Fix target address to update badaddr

current pc if exception is triggered. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 23 --- target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++-- target/riscv

[PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions

Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector instructions are the same op index as their own. And they have no functional decomp_data. So they have no functional difference from just leaving them as zero. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by

[PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h

Split RISCVCPUConfig declarations to prepare for passing it to disas. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h | 114 +- target/riscv/cpu_cfg.h | 136 + 2 files changed, 137

[PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses

Remove redundant parenthese and fix multi-line comments. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 219 +- 1 file changed, 110 insertions(+), 109 deletions(-) diff --git a

[PATCH v2 0/8] Add support for extension specific disas

Barboza) Weiwei Li (8): disas: Change type of disassemble_info.target_info to pointer target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info disas/riscv.c: Support disas for Zcm* extensions disas

[PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer

Use pointer to pass more information of target to disasembler, such as pass cpu.cfg related information in following commits. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- include/disas/dis-asm.h | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info

Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 10 +++--- target/riscv/cpu.c | 1 + 2 files

[PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions

Support disas for Z*inx instructions only when Zfinx extension is supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/disas/riscv.c b/disas

[PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions

Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas

[PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters

Fix lines with over 80 characters. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 201 +++--- 1 file changed, 140 insertions(+), 61 deletions(-) diff --git a/disas/riscv.c b/disas

Re: [PATCH 3/7] disas/riscv.c: Support disas for Zcm* extensions

On 2023/5/22 21:10, Daniel Henrique Barboza wrote: In fact, apparently checkpatch.pl is not too happy about this patch: On 5/18/23 23:19, Weiwei Li wrote: Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang

Re: [PATCH 3/7] disas/riscv.c: Support disas for Zcm* extensions

On 2023/5/22 21:00, Daniel Henrique Barboza wrote: On 5/18/23 23:19, Weiwei Li wrote: Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   disas/riscv.c | 20   1 file changed, 12

Re: [PATCH 2/7] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info

On 2023/5/22 20:54, Daniel Henrique Barboza wrote: On 5/18/23 23:19, Weiwei Li wrote: Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- I suggest split

[PATCH 4/7] disas/riscv.c: Support disas for Z*inx extensions

Support disas for Z*inx instructions only when Zfinx extension is supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 9e01810eef..a370bac6ef

[PATCH 7/7] disas/riscv.c: Remove redundant parentheses

Remove redundant parenthese and fix multi-line comments. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 219 +- 1 file changed, 110 insertions(+), 109 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index

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