Can you provide a clearer repro example of what doesn't wirk on mipsel
platform?
In last two QEMU releases mips (Wave) developers went to great lenghts
making sure both mips SIMD and mips FP instructions (in both scalar and
vector variants) are emulated properly. Some of the unit tests were
publis
I can confirm bench_simple gives the same result on both qemu-arm and my
aarch32 hardware.
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https://bugs.launchpad.net/bugs/1851095
Title:
[feature request] awareness of instructions t
appears the random number generator produces different results on 32-bit
arches, while my code seems to work fine in qemu
** Changed in: qemu
Status: New => Invalid
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Here is the same thing compiled with optimizations on
** Attachment added: "bench_simple"
https://bugs.launchpad.net/qemu/+bug/1851095/+attachment/5302825/+files/bench_simple
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https:
example binary doing double-precision exponent on 16 megs
expected output:
checksum: f181b401cd42aa7b
actual output:
checksum: 4004022b0ba624fb
** Attachment added: "bench_simple"
https://bugs.launchpad.net/qemu/+bug/1851095/+attachment/5302817/+files/bench_simple
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Can you please provide a binary (preferably statically built or with
required shared libraries attached)?
Thanks,
Laurent
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https://bugs.launchpad.net/bugs/1851095
Title:
[feature req
ok, here is a double precision exponent implementation that works on
arm32 hardware, but fails in qemu with the wrong checksum.
https://github.com/shawnl/zig-libmvec/blob/master/exp.zig
You need to build zig with the above patch-set.
I guess I am starting from a pessimistic perspective, where I h
Here is a pull request for the zig language that runs into this problems
in qemu https://github.com/ziglang/zig/pull/2945/
I have more code for validation if someone is working on this.
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