On Mon, 22 Jul 2024 at 17:51, Paolo Bonzini wrote:
>
> On Mon, Jul 22, 2024 at 4:29 PM Philippe Mathieu-Daudé
> wrote:
> > It seems this model could be simplified using .min_access_size = 8,
> > letting the core memory layer handle the % 4 byte accesses (the
> > read path is obvious, the write on
On Mon, Jul 22, 2024 at 4:29 PM Philippe Mathieu-Daudé
wrote:
> It seems this model could be simplified using .min_access_size = 8,
> letting the core memory layer handle the % 4 byte accesses (the
> read path is obvious, the write one a bit less). Nothing urgent,
> possibly a BitSizedTask.
The m
On 22/7/24 13:53, Paolo Bonzini wrote:
On Sat, Jul 20, 2024 at 4:30 PM Peter Maydell wrote:
If the HPET timer device is supposed to permit 64 bit writes and it is not
doing so, then that needs to be fixed in the HPET timer device model, by
making sure that its read/write functions correctly han
On Sat, Jul 20, 2024 at 4:30 PM Peter Maydell wrote:
> If the HPET timer device is supposed to permit 64 bit writes and it is not
> doing so, then that needs to be fixed in the HPET timer device model, by
> making sure that its read/write functions correctly handle the size=8 case
> and then setti
On Sat, 20 Jul 2024 at 08:56, TaiseiIto wrote:
>
> Before this commit, an HPET driver can not write correct values to
> comparator registers of HPET timers. When I tested my HPET driver on QEMU, I
> ovserved too early HPET interruptions. I investigated cause and found that
> QEMU didn't write high
Before this commit, an HPET driver can not write correct values to
comparator registers of HPET timers. When I tested my HPET driver on QEMU, I
ovserved too early HPET interruptions. I investigated cause and found that
QEMU didn't write higher 32 bits of comparator registers of HPET timers even
tho
