> > AFAICT, Ztso allows the forwarding in question too. Simulations with
> > the axiomatic formalization confirm such expectation:
>
> OK that seems to be what it says in:
> https://five-embeddev.com/riscv-isa-manual/latest/ztso.html
> 'In both of these memory models, it is the that allows a ha
> > > Is x86's brand of memory ordering strong enough for Ztso?
> > > I thought x86 had an optimisation where it was allowed to store forward
> > > within the current CPU causing stores not to be quite strictly ordered.
[...]
> then a bit further down, '8.2.3.5 Intra-Processor Forwarding Is Allow
* Andrea Parri (and...@rivosinc.com) wrote:
> > > > Is x86's brand of memory ordering strong enough for Ztso?
> > > > I thought x86 had an optimisation where it was allowed to store forward
> > > > within the current CPU causing stores not to be quite strictly ordered.
>
> [...]
>
> > then a bit
* Palmer Dabbelt (pal...@rivosinc.com) wrote:
> On Thu, 29 Sep 2022 12:16:48 PDT (-0700), dgilb...@redhat.com wrote:
> > * Palmer Dabbelt (pal...@rivosinc.com) wrote:
> > > Ztso, the RISC-V extension that provides the TSO memory model, was
> > > recently frozen. This provides support for Ztso on t
On Thu, 29 Sep 2022 12:16:48 PDT (-0700), dgilb...@redhat.com wrote:
* Palmer Dabbelt (pal...@rivosinc.com) wrote:
Ztso, the RISC-V extension that provides the TSO memory model, was
recently frozen. This provides support for Ztso on targets that are
themselves TSO.
Signed-off-by: Palmer Dabbel
* Palmer Dabbelt (pal...@rivosinc.com) wrote:
> Ztso, the RISC-V extension that provides the TSO memory model, was
> recently frozen. This provides support for Ztso on targets that are
> themselves TSO.
>
> Signed-off-by: Palmer Dabbelt
>
> ---
>
> diff --git a/tcg/i386/tcg-target.h b/tcg/i38
On Sat, 17 Sep 2022 01:02:46 PDT (-0700), Richard Henderson wrote:
On 9/16/22 14:52, Palmer Dabbelt wrote:
Though, honestly, I've had patches to add the required barriers sitting around
for the
last few releases, to better support things like x86 on aarch64. I should just
finish
that up.
I
On 9/16/22 14:52, Palmer Dabbelt wrote:
Though, honestly, I've had patches to add the required barriers sitting around
for the
last few releases, to better support things like x86 on aarch64. I should just
finish
that up.
I can just do that for the RISC-V TSO support? Like the cover letter
On Sat, 03 Sep 2022 17:47:54 PDT (-0700), richard.hender...@linaro.org wrote:
On 9/2/22 04:44, Palmer Dabbelt wrote:
-#define TCG_GUEST_DEFAULT_MO 0
+/*
+ * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and
+ * fetch), and WMO is approximately equivilant to Arm MCA. Rather
On 9/2/22 04:44, Palmer Dabbelt wrote:
-#define TCG_GUEST_DEFAULT_MO 0
+/*
+ * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and
+ * fetch), and WMO is approximately equivilant to Arm MCA. Rather than
+ * enforcing orderings on most accesses, just default to the target memor
Ztso, the RISC-V extension that provides the TSO memory model, was
recently frozen. This provides support for Ztso on targets that are
themselves TSO.
Signed-off-by: Palmer Dabbelt
---
My first thought was to just add the TCG barries to load/store and AMOs
that as defined by Ztso, but after po
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