On 2/19/21 11:35 PM, Peter Maydell wrote:
> This patch has been reviewed and fixes a Coverity issue;
> Philippe, are you planning to take it through your MIPS tree?
Sorry felt through the crack, now applied to mips-next (I'll send
a pull request next week).
Thanks!
>
> -- PMM
>
> On Tue, 12 Ja
This patch has been reviewed and fixes a Coverity issue;
Philippe, are you planning to take it through your MIPS tree?
-- PMM
On Tue, 12 Jan 2021 at 01:28, Jiaxun Yang wrote:
>
> Per core ISR is a set of 32-bit registers spaced by 8 bytes.
> This patch fixed calculation of it's size and also add
Reviewed-by: Huacai Chen
On Tue, Jan 12, 2021 at 9:25 AM Jiaxun Yang wrote:
>
> Per core ISR is a set of 32-bit registers spaced by 8 bytes.
> This patch fixed calculation of it's size and also added check
> of alignment at reading & writing.
>
> Signed-off-by: Jiaxun Yang
> ---
> hw/intc/loon
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.
Signed-off-by: Jiaxun Yang
---
hw/intc/loongson_liointc.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff -
