I'm not aware of any bug reports. L1 cache is typically shared between
logical threads, so it seemed reasonable to correct this.
On Fri, Oct 28, 2022 at 9:54 AM Wang, Lei wrote:
>
> On 10/10/2022 10:49 AM, Ilya Oleinik wrote:
> > For EBX bits 23 - 16 in CPUID[01] Intel's manual states:
> > "
> >
On 10/10/2022 10:49 AM, Ilya Oleinik wrote:
> For EBX bits 23 - 16 in CPUID[01] Intel's manual states:
> "
> * The nearest power-of-2 integer that is not smaller than EBX[23:16]
> is the number of unique initial APICIDs reserved for addressing
> different logical processors in a physica
For EBX bits 23 - 16 in CPUID[01] Intel's manual states:
"
* The nearest power-of-2 integer that is not smaller than EBX[23:16]
is the number of unique initial APICIDs reserved for addressing
different logical processors in a physical package. This field is
only valid if CPUID.1.EDX.H
