Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

2019-09-26 Thread Sebastian Andrzej Siewior
On 2019-09-26 13:06:34 [+0200], Paolo Bonzini wrote: > On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store > > Bypass Disable */ > > > > +#define CPUD_800_008_EBX_CLZERO(1U << 0) /* CLZERO instruction > > */

Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

2019-09-26 Thread Paolo Bonzini
On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass > Disable */ > > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction > */ > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always sav

Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

2019-09-26 Thread Paolo Bonzini
On 25/09/19 23:49, Sebastian Andrzej Siewior wrote: > The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform > and could be passed to the guest. > > Signed-off-by: Sebastian Andrzej Siewior > --- > > I tweaked the kernel to expose these flags and figured out that this is > also

[PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR

2019-09-25 Thread Sebastian Andrzej Siewior
The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform and could be passed to the guest. Signed-off-by: Sebastian Andrzej Siewior --- I tweaked the kernel to expose these flags and figured out that this is also missing in order see those bits in the guest. target/i386/cpu.c |