On Thu, May 5, 2022 at 12:30 PM nihui wrote:
>
> Ah, I admit that I haven't tested the availability of the H extension,
> I could update the new patch to only add the V extension.
>
> Regarding the motivation for this modification,
> the ncnn project uses the risc-v vector extension to optimize th
Ah, I admit that I haven't tested the availability of the H extension,
I could update the new patch to only add the V extension.
Regarding the motivation for this modification,
the ncnn project uses the risc-v vector extension to optimize the efficiency of
nn inference.
I am very happy to find th
On Wed, 04 May 2022 08:10:03 PDT (-0700), alistai...@gmail.com wrote:
On Wed, May 4, 2022 at 2:32 PM nihui wrote:
This patch brings the optional risc-v vector and hypervisor bits
in hwcap so that application could detect these isa support from
/proc/self/auxv correctly in qemu userspace mode.
On Wed, May 4, 2022 at 2:32 PM nihui wrote:
>
> This patch brings the optional risc-v vector and hypervisor bits
> in hwcap so that application could detect these isa support from
> /proc/self/auxv correctly in qemu userspace mode.
>
> Signed-off-by: Ni Hui
> ---
> linux-user/elfload.c | 3 ++-
>
This patch brings the optional risc-v vector and hypervisor bits
in hwcap so that application could detect these isa support from
/proc/self/auxv correctly in qemu userspace mode.
Signed-off-by: Ni Hui
---
linux-user/elfload.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
