Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 6/2/22 13:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do t
On 6/2/22 14:06, Frederic Barrat wrote:
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID regi
On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
l
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access for node 0 when
computing the PIR. Everyt
