Hi Alistair,
Sorry for the late reply, I was on PTO.
On Tue, Apr 18, 2023 at 4:22 AM Alistair Francis wrote:
>
> On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
> >
> > Hi Alistair,
> >
> > > > @@ -936,6 +936,11 @@ restart:
> > > > return TRANSLATE_FAIL;
> > > > }
> >
On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
>
> Hi Alistair,
>
> > > @@ -936,6 +936,11 @@ restart:
> > > return TRANSLATE_FAIL;
> > > }
> > >
> > > +/* PTE reserved bits must be cleared otherwise an exception is
> > > raised */
> > > +if (riscv_cpu_mx
Hi Alistair,
> > @@ -936,6 +936,11 @@ restart:
> > return TRANSLATE_FAIL;
> > }
> >
> > +/* PTE reserved bits must be cleared otherwise an exception is
> > raised */
> > +if (riscv_cpu_mxl(env) == MXL_RV64 && (pte & PTE_RESERVED)) {
> > +return TR
On Wed, Apr 12, 2023 at 7:18 PM Alexandre Ghiti wrote:
>
> As per the specification, in 64-bit, if any of the pte reserved bits 60-54
> is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
> Protection"), so implement this behaviour in the address translation process.
>
> Re
As per the specification, in 64-bit, if any of the pte reserved bits 60-54
is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
Protection"), so implement this behaviour in the address translation process.
Reported-by: Andrea Parri
Signed-off-by: Alexandre Ghiti
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