Re: [PATCH] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only

On 11/21/23 08:46, Peter Maydell wrote: The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can b

[PATCH] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only

The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditi