On Fri, 9 Oct 2020 at 23:36, Richard Henderson
wrote:
>
> On 10/9/20 1:48 PM, Peter Maydell wrote:
> > On Fri, 9 Oct 2020 at 15:47, Peter Maydell wrote:
> >> +tcg_gen_extr_i64_i32(t1, t2, p64);
> >
> > Oh, I forgot to mention, but it looks like extr_i64_i32
> > isn't documented in tcg/REA
On 10/9/20 1:48 PM, Peter Maydell wrote:
> On Fri, 9 Oct 2020 at 15:47, Peter Maydell wrote:
>> +tcg_gen_extr_i64_i32(t1, t2, p64);
>
> Oh, I forgot to mention, but it looks like extr_i64_i32
> isn't documented in tcg/README. Is that because it isn't
> really a TCG IR op, or just an omiss
On 10/9/20 1:47 PM, Peter Maydell wrote:
> On Fri, 9 Oct 2020 at 18:57, Richard Henderson
> wrote:
>>
>> On 10/9/20 9:47 AM, Peter Maydell wrote:
>>> +/*
>>> + * t1 is the low half of the result which goes into Rd.
>>> + * We have overflow and must set Q if the high half (t
On Fri, 9 Oct 2020 at 15:47, Peter Maydell wrote:
> +tcg_gen_extr_i64_i32(t1, t2, p64);
Oh, I forgot to mention, but it looks like extr_i64_i32
isn't documented in tcg/README. Is that because it isn't
really a TCG IR op, or just an omission?
thanks
-- PMM
On Fri, 9 Oct 2020 at 18:57, Richard Henderson
wrote:
>
> On 10/9/20 9:47 AM, Peter Maydell wrote:
> > +/*
> > + * t1 is the low half of the result which goes into Rd.
> > + * We have overflow and must set Q if the high half (t2)
> > + * is different from the sign-e
On 10/9/20 9:47 AM, Peter Maydell wrote:
> +/*
> + * t1 is the low half of the result which goes into Rd.
> + * We have overflow and must set Q if the high half (t2)
> + * is different from the sign-extension of t1.
> + */
> +t3 = tcg_temp_new_i32();
The SMLAD instruction is supposed to:
* signed multiply Rn[15:0] * Rm[15:0]
* signed multiply Rn[31:16] * Rm[31:16]
* perform a signed addition of the products and Ra
* set Rd to the low 32 bits of the theoretical
infinite-precision result
* set the Q flag if the sign-extension of Rd
wou
