Re: [PATCH] target/riscv: Add support for Zicond extension

On Tue, 21 Feb 2023 01:10:09 PST (-0800), liwei...@iscas.ac.cn wrote: The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zer

Re: [PATCH] target/riscv: Add support for Zicond extension

Reviewed-by: Frank Chang On Tue, Feb 21, 2023 at 5:10 PM Weiwei Li wrote: > The spec can be found in https://github.com/riscv/riscv-zicond. > Two instructions are added: > - czero.eqz: Moves zero to a register rd, if the condition rs2 is >equal to zero, otherwise moves rs1 to rd. > - czer

[PATCH] target/riscv: Add support for Zicond extension

The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves