Re: [PATCH] target/riscv: Fix read and write accesses to vsip and vsie

On Thu, Mar 11, 2021 at 4:49 AM Georg Kotheimer wrote: > > The previous implementation was broken in many ways: > - Used mideleg instead of hideleg to mask accesses > - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie > - Did not shift between S bits and VS bits (VSEIP <-> SE

Re: [PATCH] target/riscv: Fix read and write accesses to vsip and vsie

On Thu, Mar 11, 2021 at 4:49 AM Georg Kotheimer wrote: > > The previous implementation was broken in many ways: > - Used mideleg instead of hideleg to mask accesses > - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie > - Did not shift between S bits and VS bits (VSEIP <-> SE

[PATCH] target/riscv: Fix read and write accesses to vsip and vsie

The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Signed-off-by: Georg Kotheimer --- target/riscv/csr.c