Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

On Wed, Aug 2, 2023 at 8:50 AM Rob Bradford wrote: > > These are WARL fields - zero out the bits for unavailable counters and > special case the TM bit in mcountinhibit which is hardwired to zero. > This patch achieves this by modifying the value written so that any use > of the field will see the

Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

On Wed, Aug 2, 2023 at 8:50 AM Rob Bradford wrote: > > These are WARL fields - zero out the bits for unavailable counters and > special case the TM bit in mcountinhibit which is hardwired to zero. > This patch achieves this by modifying the value written so that any use > of the field will see the

Re: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

On Wed, Aug 2, 2023 at 5:50 AM Rob Bradford wrote: > > These are WARL fields - zero out the bits for unavailable counters and > special case the TM bit in mcountinhibit which is hardwired to zero. > This patch achieves this by modifying the value written so that any use > of the field will see the

[PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

These are WARL fields - zero out the bits for unavailable counters and special case the TM bit in mcountinhibit which is hardwired to zero. This patch achieves this by modifying the value written so that any use of the field will see the correctly masked bits. Tested by modifying OpenSBI to write