RE: [PATCH] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

2023-12-17 Thread 張哲嘉
anamicro.com; zhiwei_...@linux.alibaba.com > Subject: Re: [PATCH] target/riscv: Implement optional CSR mcontext of debug > Sdtrig extension > > On Sun, Dec 17, 2023 at 5:17 PM Alvin Chang via > wrote: > > > > The debug Sdtrig extension defines an optional CSR "mcontext

Re: [PATCH] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

2023-12-17 Thread Alistair Francis
On Sun, Dec 17, 2023 at 5:17 PM Alvin Chang via wrote: > > The debug Sdtrig extension defines an optional CSR "mcontext". Since it > is optional, this commit adds new CPU configuration > "ext_sdtrig_mcontext" and uses property "sdtrig_mcontext" to control > whether it is implemented or not. Its

[PATCH] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

2023-12-16 Thread Alvin Chang via
The debug Sdtrig extension defines an optional CSR "mcontext". Since it is optional, this commit adds new CPU configuration "ext_sdtrig_mcontext" and uses property "sdtrig_mcontext" to control whether it is implemented or not. Its predicate and read/write operations are also implemented into CSR