Re: [PATCH] target/riscv: don't enable Zfa by default

On 11/6/23 23:53, Jerry ZJ wrote: Use use mode QEMU can reproduce this Reproduce steps Compile: riscv64-unknown-elf-clang -march=rv32imac_zicsr_zifencei_zba_zbb ./test.c -o hello_rv32imac Run: qemu-riscv32 -cpu rv32,g=false,f=false,v=false,d=false,e=false,h=false,c=true,m=true,i=true,a=tru

Re: [PATCH] target/riscv: don't enable Zfa by default

Use use mode QEMU can reproduce this Reproduce steps Compile: riscv64-unknown-elf-clang -march=rv32imac_zicsr_zifencei_zba_zbb ./test.c -o hello_rv32imac Run: qemu-riscv32 -cpu rv32,g=false,f=false,v=false,d=false,e=false,h=false,c=true,m=true,i=true,a=true,Zicsr=true,Zifencei=true,zmmul=true,z

Re: [PATCH] target/riscv: don't enable Zfa by default

On 11/6/23 12:21, Jerry ZJ wrote: We do have some cases that failed. SiFive e-series cores (https://static.dev.sifive.com/SiFive-E21-Manual-v1p0.pdf ) do not have F extension (For example: rv32imc_zicsr_zifencei_zba_zbb). When we use

Re: [PATCH] target/riscv: don't enable Zfa by default

We do have some cases that failed. SiFive e-series cores (https://static.dev.sifive.com/SiFive-E21-Manual-v1p0.pdf) do not have F extension (For example: rv32imc_zicsr_zifencei_zba_zbb). When we use the corresponding extension options to configure QEMU, i.e., rv32, i=true, m=true, a=true, c=tru

Re: [PATCH] target/riscv: don't enable Zfa by default

On 11/6/23 08:14, Jerry Zhang Jian wrote: - Zfa requires F, we should not assume all CPUs have F extension support. We do not have a case where this happen, do we? The default CPUs have F enabled (see misa_ext_cfgs[] in target/riscv/tcg/tcg-cpu.c), so zfa being enable isn't a problem for

[PATCH] target/riscv: don't enable Zfa by default

- Zfa requires F, we should not assume all CPUs have F extension support. Signed-off-by: Jerry Zhang Jian --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..c9f11509c8 100644 --- a/target/riscv/cp