On Sat, Feb 20, 2021 at 12:12 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/19/21 1:59 AM, frank.ch...@sifive.com wrote:
> > +/* Skip mem_idx bits */
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
>
> Why not just add the mem_idx field to the list?
>
> The separation between the FIEL
On 2/19/21 1:59 AM, frank.ch...@sifive.com wrote:
> +/* Skip mem_idx bits */
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
Why not just add the mem_idx field to the list?
The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and will
be a continuing source of errors.
r~
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 11 ++-
1 fil
