Re: [RESEND PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

2022-04-06 Thread Alistair Francis
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li wrote: > > The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, > EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' > > So the start byte for vstart != 0 should take sew into account > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang

Re: [RESEND PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

2022-03-30 Thread Alistair Francis
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li wrote: > > The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, > EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' > > So the start byte for vstart != 0 should take sew into account > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang

[RESEND PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

2022-03-29 Thread Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte for vstart != 0 should take sew into account Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 8 +--- 1 file cha

[PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

2022-03-29 Thread Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte for vstart != 0 should take sew into account Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 8 +--- 1 file cha