Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-07-07 Thread Alistair Francis
On Thu, Jun 24, 2021 at 11:48 PM Jose Martins wrote: > > > > +static const target_ulong vs_delegable_excps = delegable_excps & > > > +~((1ULL << (RISCV_EXCP_S_ECALL)) | > > > > > +(1ULL << (RISCV_EXCP_VS_ECALL)) | > > > +(1ULL << (RISCV_EXCP_M_ECALL)) | > > > > These two are both read

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-06-24 Thread Jose Martins
> > +static const target_ulong vs_delegable_excps = delegable_excps & > > +~((1ULL << (RISCV_EXCP_S_ECALL)) | > > > +(1ULL << (RISCV_EXCP_VS_ECALL)) | > > +(1ULL << (RISCV_EXCP_M_ECALL)) | > > These two are both read only 0, shouldn't they not be included in this list? > > > static

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-06-10 Thread Alistair Francis
On Sun, May 23, 2021 at 1:59 AM Jose Martins wrote: > > The specification mandates for certain bits to be hardwired in the > hypervisor delegation registers. This was not being enforced. > > Signed-off-by: Jose Martins > --- > target/riscv/csr.c | 13 +++-- > 1 file changed, 11

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-05-27 Thread LIU Zhiwei
Reviewed-by: LIU Zhiwei Zhiwei On 5/22/21 11:59 PM, Jose Martins wrote: The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins --- target/riscv/csr.c | 13 +++-- 1 file changed,

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-05-27 Thread LIU Zhiwei
On 5/26/21 1:50 AM, Jose Martins wrote: We can use it directly if only one macro VS_MODE_INTERRUPTS. I wrote it like this to be more coherent with what was already there which also makes it more readable. Furthermore, the compiler will just probably optimize the variable away, right? Hi

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-05-25 Thread Jose Martins
> We can use it directly if only one macro VS_MODE_INTERRUPTS. I wrote it like this to be more coherent with what was already there which also makes it more readable. Furthermore, the compiler will just probably optimize the variable away, right? > I didn't find that the RISCV_EXCP_VS_ECALL

Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-05-25 Thread LIU Zhiwei
On 5/22/21 11:59 PM, Jose Martins wrote: The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins --- target/riscv/csr.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-)

[PATCH] target/riscv: hardwire bits in hideleg and hedeleg

2021-05-22 Thread Jose Martins
The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins --- target/riscv/csr.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c