From: Iris Chen <irische...@gmail.com> Hey everyone,
My patch adds the W# pin and SRWD bit which work together to control the status register write ability. Accordingly, when W# is low and SRWD bit is high, hardware protection mode (HPM) is initiated. All other cases result in software protection. Acceptance tests have been added to verify all four scenarios: it tests the ability to write to SRWD depending on whether write protection is set. Thanks, Iris Iris Chen (1): hw: m25p80: add W# pin and SRWD bit for write protection hw/block/m25p80.c | 72 +++++++++++++++++++++++++++++++++++ tests/qtest/aspeed_smc-test.c | 62 ++++++++++++++++++++++++++++++ 2 files changed, 134 insertions(+) -- 2.30.2