On Thu, Nov 30, 2023 at 3:05 AM Max Chou wrote:
>
> The ratified v1.0 version of RISC-V V spec section 16.6 says that
> `The instructions operate as if EEW=SEW.`.
>
> So the whole vector register move instructions depend on the vtype
> register that means the implementation needs to be fixed to
The ratified v1.0 version of RISC-V V spec section 16.6 says that
`The instructions operate as if EEW=SEW.`.
So the whole vector register move instructions depend on the vtype
register that means the implementation needs to be fixed to raise an
illegal-instruction exception when vtype.vill=1, as
