I'm implementing the non-JTAG portion of FEAT_Debugv8p2, which is just making sure that CONTEXTIDR_EL2 is present, even if VHE is not enabled. Then Debugv8p4 is a trivial extension that only touches the JTAG interface, so turn that on too.
I've got some cleanups to the setting of isar features for max. I'm implementing a minimal version of FEAT_RAS, which has no source of physical SErrors and thus no need for Error Records. It does implement virtual SErrors, which can be injected by the hypervisor. Since we have no physical SErrors, FEAT_IESB is a nop. Finally, I'll note that with Peter's GICv4 work, we have all of the parts necessary to implement the cortex-a76. r~ Richard Henderson (16): target/arm: Add isar predicates for FEAT_Debugv8p2 target/arm: Adjust definition of CONTEXTIDR_EL2 target/arm: Update qemu-system-arm -cpu max to cortex-a57 target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max target/arm: Split out arm32_max_features target/arm: Annotate arm_max_initfn with FEAT identifiers target/arm: Use field names for manipulating EL2 and EL3 modes target/arm: Enable FEAT_Debugv8p2 for -cpu max target/arm: Enable FEAT_Debugv8p4 for -cpu max target/arm: Add isar_feature_{aa64,any}_ras target/arm: Add minimal RAS registers target/arm: Enable SCR and HCR bits for RAS target/arm: Implement virtual SError exceptions target/arm: Implement ESB instruction target/arm: Enable FEAT_RAS for -cpu max target/arm: Enable FEAT_IESB for -cpu max target/arm/cpu.h | 33 +++++++ target/arm/helper.h | 1 + target/arm/internals.h | 10 +++ target/arm/syndrome.h | 5 ++ target/arm/a32.decode | 16 ++-- target/arm/t32.decode | 18 ++-- target/arm/cpu.c | 61 ++++++++++--- target/arm/cpu64.c | 150 ++++++++++++-------------------- target/arm/cpu_tcg.c | 166 ++++++++++++++++++++++-------------- target/arm/helper.c | 170 +++++++++++++++++++++++++++++++++++-- target/arm/op_helper.c | 45 ++++++++++ target/arm/translate-a64.c | 7 ++ target/arm/translate.c | 10 +++ 13 files changed, 504 insertions(+), 188 deletions(-) -- 2.25.1