On 3/5/21 6:35 AM, Peter Maydell wrote:
None of these I36nn section numbers match up with the current Arm ARM,
incidentally.
No, they're off the A.a document.
#define FMT_I3611(U, OPCODE) (0x5e200400 | ((U) << 29) | ((OPCODE) << 11))
and then
I3611_SQADD = FMT_I3611(0, 0b1),
I3
On Tue, 2 Mar 2021 at 18:00, Richard Henderson
wrote:
>
> For some vector operations, "1D" is not a valid type, and there
> are separate instructions for the 64-bit scalar operation.
>
> Tested-by: Stefan Weil
> Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
> Fixes: 14e4c1e2355 ("tcg/aarc
For some vector operations, "1D" is not a valid type, and there
are separate instructions for the 64-bit scalar operation.
Tested-by: Stefan Weil
Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
Signed-off-by: Richard Henderson
---
