Re: [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600

2019-09-19 Thread Joel Stanley
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater wrote: > > The AST2600 timer replaces control register 2 with a interrupt status > register. It is set by hardware when an IRQ occurs and cleared by > software. > > Modify the vmstate version to take into account the new fields. > > Based on previous

[Qemu-devel] [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600

2019-09-18 Thread Cédric Le Goater
The AST2600 timer replaces control register 2 with a interrupt status register. It is set by hardware when an IRQ occurs and cleared by software. Modify the vmstate version to take into account the new fields. Based on previous work from Joel Stanley. Signed-off-by: Cédric Le Goater ---