Re: [PATCH 1/1] hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables

2024-10-14 Thread Jonathan Cameron via
On Mon, 14 Oct 2024 11:09:12 +0100 Jonathan Cameron via wrote: > On Fri, 27 Sep 2024 10:17:43 +0100 > wrote: > > > From: Shiju Jose > > > > CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS) > > control feature. > > > > ECS log capabilities field in following ECS ta

Re: [PATCH 1/1] hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables

2024-10-14 Thread Jonathan Cameron via
On Fri, 27 Sep 2024 10:17:43 +0100 wrote: > From: Shiju Jose > > CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS) > control feature. > > ECS log capabilities field in following ECS tables, which is common for all > memory media FRUs in a CXL device. > > Fix struct

[PATCH 1/1] hw/cxl/cxl-mailbox-utils: Fix for device DDR5 ECS control feature tables

2024-09-27 Thread shiju . jose--- via
From: Shiju Jose CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS) control feature. ECS log capabilities field in following ECS tables, which is common for all memory media FRUs in a CXL device. Fix struct CXLMemECSReadAttrs and struct CXLMemECSWriteAttrs to make log