/m25p80: Fix Numonyx dummy cycle register
behavior
Hi Joe,
On Tue, Sep 29, 2020 at 05:28:35PM -0700, Joe Komlodi wrote:
> Numonyx chips determine the number of cycles to wait based on bits 7:4
> in the volatile configuration register.
>
> However, if these bits are 0x0 or 0xF, t
Hi Joe,
On Tue, Sep 29, 2020 at 05:28:35PM -0700, Joe Komlodi wrote:
> Numonyx chips determine the number of cycles to wait based on bits 7:4 in the
> volatile configuration register.
>
> However, if these bits are 0x0 or 0xF, the number of dummy cycles to wait is
> 10 on a QIOR or QIOR4 command,
Numonyx chips determine the number of cycles to wait based on bits 7:4 in the
volatile configuration register.
However, if these bits are 0x0 or 0xF, the number of dummy cycles to wait is
10 on a QIOR or QIOR4 command, or 8 on any other currently supported
fast read command. [1]
[1] http://www.mi
