Re: [PATCH 1/2] target/i386: fix cmpxchg with 32-bit register destination

2022-09-14 Thread Paolo Bonzini
On 9/12/22 09:55, Richard Henderson wrote:  * Compute... Why bother passing NULL, and fixing it up at each use... +static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0) +{ +    gen_op_deposit_reg_v(s, ot, reg, NULL, t0);   } ... when you can just as easily pass in the

Re: [PATCH 1/2] target/i386: fix cmpxchg with 32-bit register destination

2022-09-12 Thread Richard Henderson
On 9/11/22 23:26, Paolo Bonzini wrote: +/* Compute the result of writing t0 to the OT-sized register REG. + * + * If DEST is NULL, store the result into the register and return the + * register's TCGv. + * + * If DEST is not NULL, store the result into DEST and return the + * register's TCGv. +

[PATCH 1/2] target/i386: fix cmpxchg with 32-bit register destination

2022-09-11 Thread Paolo Bonzini
Unlike the memory case, where "the destination operand receives a write cycle without regard to the result of the comparison", rm must not be touched altogether if the write fails, including not zero-extending it on 64-bit processors. This is not how the movcond currently works, because it is