Re: [PATCH 1/2] tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns

2024-01-19 Thread Philippe Mathieu-Daudé
On 17/1/24 22:36, Richard Henderson wrote: While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v16,

Re: [PATCH 1/2] tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns

2024-01-17 Thread Richard Henderson
On 1/18/24 17:50, Thomas Huth wrote: Do you want to take it through our TCG branch or shall I pick it up for my s390x branch? I can take it through tcg. r~

Re: [PATCH 1/2] tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns

2024-01-17 Thread Thomas Huth
On 17/01/2024 22.36, Richard Henderson wrote: While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v

[PATCH 1/2] tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns

2024-01-17 Thread Richard Henderson
While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v16,16 Cc: qemu-sta...@nongnu.org Reported-by: Mic