On 2023-09-14 19:39, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:23 AM AEST, Glenn Miles wrote:
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register
On Wed Sep 13, 2023 at 6:23 AM AEST, Glenn Miles wrote:
> This commit is preparatory to the addition of Branch History
> Rolling Buffer (BHRB) functionality, which is being provided
> today starting with the P8 processor.
>
> BHRB uses several SPR register fields to control whether or not
> a
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be
On 9/12/23 22:00, Glenn Miles wrote:
Sorry, this is my first attempt at sending out a patch and it looks like only
part of the patch made it. Until I can figure out what I did wrong, please
ignore this patch.
I didn't get patches 2-4. Patch 1 looked good though. Please resend.
Thanks,
C.
Sorry, this is my first attempt at sending out a patch and it looks like
only part of the patch made it. Until I can figure out what I did
wrong, please ignore this patch.
Thanks,
Glenn Miles
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be
